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Showing 1 to 6 of 6 for “"software-hardware co-design"”.

  1. Software-Hardware Co-design For Deep Learning Model Acceleration

    … sizes and numbers of operations. However, it becomes a great challenge to deploy modern DNNs on mobile and edge devices because of their limited memory, computation resources and battery energy. This dissertation seeks to address these challenges by advancing and integrating techniques from both …

    duke Repository record for Software-Hardware Co-design For Deep Learning Model Acceleration (opens in a new tab)

  2. Oreo: Protecting ASLR Against Microarchitectural Attacks

    … prominently deployed mitigations against memory corruption attacks. ASLR randomly shuffles program virtual addresses to prevent attackers from knowing the location of program contents in memory. Microarchitectural side channels have been shown to defeat ASLR through various hardware mechanisms. …

    mit Repository record for Oreo: Protecting ASLR Against Microarchitectural Attacks (opens in a new tab)

  3. Dynamic binary translation from x86-32 code to x86-64 code for virtualization

    … performance of virtual machines and simplify the design of the virtual machine monitor by running 32-bit x86 operating systems in x86-64 mode. In order to do so, 32-bit operating system binary code is translated into x86-64 binary code via "widening binary translation"; x86-32 code is "widened" …

    mit Repository record for Dynamic binary translation from x86-32 code to x86-64 code for virtualization (opens in a new tab)

  4. Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems

    The Internet of Things (IoT) consists of an ever-growing network of wireless-connected electronic devices which are always collecting, processing and communicating data. While the IoT has inspired many new applications, these embedded devices have unique security challenges, thus making IoT …

    mit Repository record for Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems (opens in a new tab)

  5. Verification and Performance of the DeNovo cache coherence protocol

    With the advent of multicores, parallel programming has gained a lot of importance. For parallel programming to be viable for the predicted hundreds of cores per chip, shared memory programming languages and environments must evolve to enforce disciplined practices like ``determinism-by-default …

    uiuc Repository record for Verification and Performance of the DeNovo cache coherence protocol (opens in a new tab)

  6. Hardware-Software Co-Design for Sensor Nodes in Wireless Networks

    … tools for analyzing and evaluating different design options for wireless sensor networks (sensornets) and hence, have been intensively studied in the past decades. However, existing simulators only support evaluations of protocols and software aspects of sensornet design. They cannot …

    vt Repository record for Hardware-Software Co-Design for Sensor Nodes in Wireless Networks (opens in a new tab)