Global ETD Search

Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.

Results

Showing 1 to 20 of 78 for “"simd"”.

  1. SIMD column-parallel polygon rendering

    Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.

    mit Repository record for SIMD column-parallel polygon rendering (opens in a new tab)

  2. Compiling Vector Programs for SIMD Devices

    Made available in DSpace on 2015-09-25T20:20:14Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3242971.pdf: 3661089 bytes, checksum: 4441fcd295b39b414c7c04dc3713b189 (MD5) Previous issue date: 2006

    uiuc Repository record for Compiling Vector Programs for SIMD Devices (opens in a new tab)

  3. SIMD pipelined processor implemented on a FPGA

    … multiplication functionality and single-cycle SIMD instructions. The architecture contains parameters for easy modification of SIMD units depending on the needs of the processor. The SIMD architecture was designed with distributed memory so that every memory unit received the same address. This …

    unm Repository record for SIMD pipelined processor implemented on a FPGA (opens in a new tab)

  4. Computing the fast Fourier transform on SIMD microprocessors

    … signal on single-instruction, multiple-data (SIMD) microprocessors faster than or very close to the speed of state of the art libraries such as FFTW (“Fastest Fourier Transform in the West”), SPIRAL and Intel Integrated Performance Primitives (IPP). The conjugate-pair algorithm has advantages …

    waikato-masters Repository record for Computing the fast Fourier transform on SIMD microprocessors (opens in a new tab)

  5. A SIMD architecture for hard real-time systems

    … In this work I present Sim-D: a wide-SIMD architecture for hard real-time systems. Similar to GPUs, Sim-D performs hardware strip-mining to schedule the work for a compute kernel in entities called work-groups. Sim-D schedules the work for each work-group as a sequence of …

    cambridge Repository record for A SIMD architecture for hard real-time systems (opens in a new tab)

  6. VeGen: A Vectorizer Generator for SIMD and Beyond

    … on targeting single instruction multiple data (SIMD) instructions. However, these auto-vectorization techniques are not sufficiently powerful to model non-SIMD vector instructions, which can accelerate applications in domains such as image processing, digital signal processing, and machine …

    mit Repository record for VeGen: A Vectorizer Generator for SIMD and Beyond (opens in a new tab)

  7. Simulation of massively parallel SIMD architectures using FPGA support

    Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.

    mit Repository record for Simulation of massively parallel SIMD architectures using FPGA support (opens in a new tab)

  8. A flexible compilation infrastructure for VLIW and SIMD architectures

    Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.

    mit Repository record for A flexible compilation infrastructure for VLIW and SIMD architectures (opens in a new tab)

  9. H-SIMD machine : configurable parallel computing for data-intensive applications

    … on field-programmable gate arrays (FPGAs). H-SIMD targets data-intensive applications for FPGA-based system designs. The H-SIMD machine is associated with a hierarchical instruction set architecture (HISA) which is developed for each application. The main objectives of this work are to …

    njit Repository record for H-SIMD machine : configurable parallel computing for data-intensive applications (opens in a new tab)

  10. Design and implementation of a PowerPC backend with optimizations for the AltiVec SIMD processor

    Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.

    mit Repository record for Design and implementation of a PowerPC backend with optimizations for the AltiVec SIMD processor (opens in a new tab)

  11. Speculative Vectorization with Selective Replay

    … revisions. Single Instruction Multiple Data (SIMD) execution, where a single instruction operates on multiple data items, offers higher performance and lower energy consumption. Unlike other types of execution that need to fetch, decode and execute one instruction per data operation, SIMD

    cambridge Repository record for Speculative Vectorization with Selective Replay (opens in a new tab)

  12. Applying Source Level Auto-Vectorization to Aparapi Java

    … data parallel single instruction multiple data (SIMD) instructions, as well as parallel compute cores in both central processing units (CPUs) and graphics processing units (GPUs). While these hardware enhancements offer potential performance enhancements, programs must be re-written to take …

    vt Repository record for Applying Source Level Auto-Vectorization to Aparapi Java (opens in a new tab)

  13. Techniques to maximize memory bandwidth on the Rigel compute accelerator

    … processor chips. Currently GPUs that use wide SIMD are the primary implementations in this space. Many applications targeted to this space are performance limited by the memory all, so comparing the memory system performance of Rigel and GPUs is desirable. Memory controllers in GPUs attempt to …

    uiuc Repository record for Techniques to maximize memory bandwidth on the Rigel compute accelerator (opens in a new tab)

  14. Xmalloc: a scalable lock-free dynamic memory allocator for many-core machines

    … of processors and number of vector units in one SIMD processor. A truly scalable algorithm should take advantage for both venues. However, most of past research, on scalable memory allocators such as atomic operation based lock-free algorithms, can be scalable with number of processors growing, …

    uiuc Repository record for Xmalloc: a scalable lock-free dynamic memory allocator for many-core machines (opens in a new tab)

  15. High-performance matrix multiplication on Intel and FGPA platforms

    … factor in this case. Also, the results show that SIMD platforms, such as Intel Xeon and SIMD extensions and an in-house developed VP (Vector co-Processor), for an FPGA, can accelerate matrix multiplication substantially. It is even shown that the VP runs faster than MKL (Intel's optimized Math …

    njit Repository record for High-performance matrix multiplication on Intel and FGPA platforms (opens in a new tab)

  16. An interface between single assignment C and vector Pascal

    … but it doesn’t contain any utilization of SIMD technology, and Vector Pascal implements array operations with the help of SIMD instruction sets of modern general processors. Thus my hypothesis is that this combination will let the program enjoy higher run-time performance compared to the …

    glasgow Repository record for An interface between single assignment C and vector Pascal (opens in a new tab)

  17. Dynamic loop vectorization for executing OpenCL kernels on CPUs

    … via loop-based serialization or in parallel via SIMD vectorization. SIMD vectorization is particularly difficult where control divergence is present. This thesis proposes a technique for transforming divergent loops in OpenCL kernels such that vectorization opportunities can be extracted when …

    uiuc Repository record for Dynamic loop vectorization for executing OpenCL kernels on CPUs (opens in a new tab)

  18. Simplified vector-thread architectures for flexible and efficient data-parallel accelerators

    … vector single-instruction multiple-data (vector-SIMD) pattern, the single-instruction multiple-thread (SIMT) pattern, and the vector-thread (VT) pattern. Our recently proposed VT pattern includes many control threads that each manage their own array of microthreads. The control thread uses vector …

    mit Repository record for Simplified vector-thread architectures for flexible and efficient data-parallel accelerators (opens in a new tab)

  19. Automatically Optimizing Tree Traversal Algorithms

    … <p>Modern commodity processors support SIMD instructions, and using these instructions to process multiple traversals at once has the potential to provide substantial performance improvements. Unfortunately tree algorithms often feature highly diverging traversals which inhibit efficient …

    purdue-thes Repository record for Automatically Optimizing Tree Traversal Algorithms (opens in a new tab)

  20. A parallel algorithm for simple roots of polynomials

    … evaluation. The method is designed for an SIMD parallel computer. The algorithm is compared to two other frequently used polynomial root finders, the Jenkins-Traub algorithm and Laguerre’s method.

    vt Repository record for A parallel algorithm for simple roots of polynomials (opens in a new tab)

Page 1 of 4