Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 21 for “"serial link"”.
-
Design of all digital phase-locked loop in serial link communication
… topic that is gaining interest. In high speed links, clocking circuitry is vital, and phase-locked loop (PLL) is at the heart of every on-chip clocking circuit. The clocking circuitry needs to be robust, low-power and fast in order to fulfill the increasing demand for high data rate links. The …
-
Design of a phase locked loop based clocking circuit for high speed serial link applications
… need to scale accordingly and clever I/O links need to be developed. The most crucial component of any high-speed I/O link is the clocking circuitry: clock generator at the transmit (TX) end and clock-recovery unit on the receive (RX) end. This thesis provides an in-depth tutorial on …
-
Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology
… equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS technology. Two types of equalizers are implemented: a continuous time linear equalizer (CTLE) and a 1-tap full-rate decision feedback equalizer (DFE). The combined CTLE and DFE architecture is simulated with an rms receiver clock …
-
Toward realizing power scalable and energy proportional high-speed wireline links
… of cloud computing has placed high-speed serial links at the center stage. Due to saturating energy efficiency improvements over the last five years, increasing the data throughput comes at the cost of power consumption. Conventionally, serial link power can be reduced by optimizing …
-
A Framework for Real-Time Path Planning in Changing Environments
… evaluate an implementation of our approach for serial-link manipulators with up to 20 joints.
-
Design and modelling of clock and data recovery integrated circuit in 130 nm CMOS technology for 10 Gb/s serial data communications
… as the Verilog-A modeling of an asynchronous serial link based chip to chip communication system incorporating the proposed concept. The proposed design was implemented and fabricated using the 130 nm CMOS technology offered by UMC (United Microelectronics Corporation). Different PLL-based CDR …
-
Serialization and asynchronous techniques for reliable network-on-chip communication
… the development and validation of efficient links that improve NoC performance, power consumption and reliability. There is emphasis on low-level simulation and validation of the NoC links throughout and gate level circuits are given to provide practical implementations.<br/>The first part of …
-
Energy-efficient systems for information transfer and processing
… converter (ADC)-based multi-Gb/s serial link receivers, the power dissipation is dominated by the ADC. ADCs in serial links employ signal-to-noise-and-distortion-ratio (SNDR) and effective-number-of-bits (ENOB) as performance metrics because these are the standard for generic ADC …
-
Randomised shuffle and applied misinformation: An enhanced model for contact-based smart-card serial data transfer
… read/write machines via a single bi-directional serial link. This link is easy to monitor with inexpensive equipment and resources, enabling captured data to be removed for later examination. In many contact-based smart-cards the logical abilities are provided by eight-bit microcontroller units …
-
Design and Implementation of a Practical FLEX Paging Decoder
… by the decoder to an external computer through a serial link for bit processing and storage. A FLEX transmitter will send randomly generated data so that a bit error rate (BER) calculation can be made at a PC. Each receiver'9s noise power and noise bandwidth will be measured so that noise spectral …
-
Design of a clock and data recovery circuit in 65 nm technology
… communication technology with CMOS. A high-speed serial link (HSSL) can help meet this goal. The clock and data recovery circuit (CDR) is a critical component of the HSSL. CDR is built on the receiver end of the link after proper equalization. Its purpose is to extract clock signal which is not …
-
Transparent Asynchronous Transmitter Receiver Interface (TAXI) communications for fiber optic data links
Serial or parallel data links have been the primary tools of data transfer across physical layer boundaries for point-to-point communication systems. However there exists a tradeoff between these two kinds of data transfer mechanisms based on their cost-effectiveness and complexity. A recent …
-
Development of an experimental platform for architectural-scale robotics : the Digital Construction Platform
… Construction Platform, or DCP. The DCP is a serial-link micro-macro manipulator robot intended for architectural-scale fabrication tasks, originally conceived of and presented by Keating in [1]. It is envisioned primarily as a platform for experimentation in automated construction, rather …
-
Modeling, estimation and control for serial flexible robot arms
… inefficient, and potentially dangerous serial link manipulators. Industry has been reluctant to move towards lighter, and therefore inherently more flexible manipulators, despite the potential benefits of lower costs, increased throughput and improved safety. Advancements in data …
-
Clock synthesizer design with analog and digital phase locked loop
… demand for data rate in wireless and wireline links into multi-Gbps ranges. In order to fulfill the increasing demand for high data rate links, the performance of the I/O channel needs to scale proportionally. But, due to the lag in interconnect scaling and PCB material improvements, the …
-
A multi-user process interface system for a process control computer
… communicating with a host (the PDP-11/23) via a serial line. Hardware to drive a 600-metre serial link at 9600 baud between the PDP-11/23 and the Media interface was designed and built. The software system on the host, written in RTL/2, holds-all data from the interface in a resident common …
-
High-Speed Serial Data Link Design and Simulation
… describes the modeling and simulation of 10 Gb/s serial data link architectures. The first architecture uses a continuous-time receiver equalizer to equalize a channel with known frequency response. The second incorporates an adaptive decision feedback equalizer (DFE) for use in unknown or …
-
Circuit architectures for high speed CMOS clock and data recovery circuits
… a major impediment to increasing data rates in a serial communication system. Several CDR architectures have been proposed to ensure that the performance is comparable to traditional discrete SiGe, InP devices. In this thesis, three different CDR circuit architectures are designed in a 180 nm CMOS …
-
Design of energy-efficient high-speed wireline transceiver
… the need for energy-efficient high-speed I/O serial links. However, the rate at which the energy efficiency of serial links is improving is much slower than the rate at which the required data transfer bandwidth is increasing. This dissertation explores two design approaches for …
-
Dynamic power management for computing and communication
… for short-reach on-board chip to chip links. In this thesis, we explore power scaling techniques for on-chip high-speed links. To this end, A 10Gb/s rapid-on/off on-chip link transceiver is presented to demonstrate the architecture and circuit techniques to improve energy efficiency …
Page 1 of 2