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Showing 1 to 2 of 2 for “"sampling clock skew"”.
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SHA-less pipeline ADC design with sampling clock skew calibration
… (SHA). However, in a SHA-less architecture the sampling clock skew between the sub-ADC and the multiplying digital-to-analog converter (MDAC) in the pipeline first stage results in gross conversion errors at high input frequencies. This skew effect is aggravated in a SHA-less multi-bit-per-stage …
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Calibration of sampling clock skew in high-speed, high-resolution time-interleaved ADCs
… and high-resolution ADCs. In order to raise the sampling rates of ADCs in a power efficient manner, time-interleaving is an essential technique, whereby N ADC channels, each operating at a sampling frequency of fs, are used to achieve an effective conversion rate of N - fs. While …