Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 24 for “"register transfer level (RTL)"”.
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Timing verification and synthesis of circuits for delay fault testability
… The timing verification algorithm uses Register Transfer Level (RTL) descriptions to eliminate false paths (non-sensitizable) due to redundancy, reconvergent fanout, and control signal constraints. The RTL descriptions help to prune the search space because only valid paths are …
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Enhancing quality of assertion generation: methods for automatic assertion generation and evaluation
… for automatically generating and evaluating register transfer level (RTL) assertions. We detail the GoldMine methodology and each of its data mining algorithms. We introduce the Best-Gain Decision Forest algorithm to mine concise RTL assertions. We develop an assertion ranking methodology. We …
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Goldmine: An integration of data mining and static analysis for automatic generation of hardware assertions
… of data mining and static analysis of the Register Transfer Level (RTL) design. The RTL design is first simulated to generate data about the design’s dynamic behavior. The generated data is then mined for ""candidate assertions"" that are likely to be invariants. We present both a decision …
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Timing distribution in VHDL behavioral models
… device are made available. Also, due to the Register Transfer Level (RTL) of abstraction, which is represented by a process model graph, there is close correspondence with the actual device being modeled. Thus a better insight into the timing problems is provided and synthesis is possible …
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Guiding RTL Test Generation Using Relevant Potential Invariants
… test vectors for design validation at the Register Transfer Level (RTL). Providing useful guidance to the test generator for such techniques is critical. In our approach, we provide guidance by exploiting potential invariants in the design. These potential invariants are obtained using …
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High-Level CSP Model Compiler for FPGAs
… time has subsequently raised a need for high-level synthesis design methodologies that raise the design to a higher level of abstraction. Higher level of abstraction helps in increasing the predictability and productivity of the design and reduce the number of bugs due to human-error. It also …
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Guarded atomic actions and refinement in a system-on-chip development flow: bridging the specification gap with Event-B
… and verification flows, languages and tools. The Register Transfer Level (RTL)description, which forms the input for synchronous, logic synthesis-driven design is at too low a level of abstraction for efficient architectural exploration and re-use. The existing methods for taking a high-level …
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RTL Functional Test Generation Using Factored Concolic Execution
… test generation framework that uses it for high-level functional test generation. The test generation effort is visualized as the systematic unraveling of the control-flow response of the design over multiple (factored) explorations. We begin by transforming the Register Transfer Level (RTL) …
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Coverage analysis for assertions and emulation based verification
… by the test suite code coverage reported by Register Transfer Level (RTL) simulators and the other by assertion correctness in the context of formal verification. We present efficient algorithms to compute coverage with respect to the proposed metrics by analyzing the Control Flow Graph (CFG) …
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Accelerating RTL Simulation Through Fine-grained Task Dataflow and Selective Execution
… design space. Simulation can happen at different levels of abstraction. In this work we focus on Register-Transfer-Level (RTL) simulation. While RTL simulators are frequently used in development due to their quick compilation times, their runtime performance is slow. This is because as the designs …
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Increasing Branch Coverage with Dual Metric RTL Test Generation
In this thesis, we present a new register-transfer level (RTL) test generation method that makes use of two coverage metrics, Branch Coverage, and Mutation Coverage across two stages, to cover hard-to-reach points previously unreached. We start with a preprocessing stage by converting the RTL …
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Improving Branch Coverage in RTL Circuits with Signal Domain Analysis and Restrictive Symbolic Execution
… towards efficient test stimuli generation for Register Transfer Level (RTL) circuits. However, stimuli generation frameworks are still not capable of generating effective stimuli for all circuits. Some of the limiting factors are 1) It is hard to ascertain if a branch in the RTL code is …
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HE-MT6D: A Network Security Processor with Hardware Engine for Moving Target IPv6 Defense (MT6D) over 1 Gbps IEEE 802.3 Ethernet
… Property (IP) block developed in full Register Transfer Level (RTL) and is the first hardware-oriented design of MT6D. Major contributions of HE-MT6D include the complete separation of the data and control planes, development of a nonlinear Complex Instruction Set Computer (CISC) …
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Task Scheduling Techniques to Accelerate RTL Simulation
… While simulation can happen at different levels of abstraction, Register-Transfer-Level (RTL) simulation is the usual bottleneck in chip design, as it is needed for ongoing debugging and evaluation. Current simulators scale poorly across CPU cores, because they are unable to exploit the …
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Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration
… process migration to the acceleration of Register Transfer Level (RTL) circuit simulation is developed and analyzed. RTL code can exhibit a form of locality of reference such that executing processes tend to be executed again. This property is termed executive temporal locality, and it can …
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Branch Guided Metrics for Functional and Gate-level Testing
… most of the design activity has moved to the register transfer level (RTL), test methodologies at the RTL have been gaining momentum. We present a novel functional test generation framework for functional test generation at RTL. A popular software-based metric for measuring the effectiveness …
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Dafny-HLS: verified and optimized high-level synthesis via MLIR with LLM-assisted bug repair
High-Level Synthesis (HLS) improves hardware design productivity by generating Register-Transfer Level (RTL) from high-level language descriptions (e.g., C/C++). While recent MLIR-based HLS frameworks enable multi-level optimization and automated design space exploration, they are based on the …
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Hardware IP Classification through Weighted Characteristics
… known as Structural Checking which analyzes Register-Transfer Level (RTL) and gate-level soft IPs. Given an unknown IP, the Structural Checking tool will break down the design primary ports and internal signals into assets that fall into six characteristics. These characteristics organize how …
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Coverage-directed validation of hardware models
… typically start with writing behavioral or Register-Transfer level (RTL) description of the system functionality using a Hardware Description Language (HDL). After that they transform the HDL description to the gate-level, transistor level, and finally generate mask-level layout which is …
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High Level Power Estimation and Reduction Techniques for Power Aware Hardware Design
… These factors have necessitated the abstraction level of design-entry of hardware systems to be raised beyond the Register-Transfer-Level (RTL) to Electronic System Level (ESL). However, power envelope on the designs due to packaging and other thermal limitations, and the energy envelope due to …
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