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Showing 1 to 2 of 2 for “"refresh power"”.
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Exploiting on-chip memory concurrency in 3d manycore architectures
… end, we propose an extremely low-latency, low-power, high-radix router and present its various versions for different network typologies and configurations. We also explore optimizations and techniques to reduce the traffic in the network. Second, we propose a reorganization of the memory …
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Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies
… use dynamic energy ever more efficiently, static power consumption becomes a major concern. In particular, in a large manycore running at a low voltage, leakage in on-chip memory modules contributes substantially to the chip’s power draw. This is unfortunate given that, intuitively, the large …