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Showing 1 to 3 of 3 for “"quadrupler"”.
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High-performance reference frequency generation techniques
… locking clock multiplier driven by the proposed quadrupler is used to demonstrate the efficacy of the quadrupler. Fabricated in a 65nm CMOS process, the proposed clock multiplier occupies an active area of 0.16mm2 and achieves 366fsrms integrated jitter at 4.752GHz output frequency while …
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Systems and circuits for broadband contactless and wireline transceivers
… of a ring-oscillator-based PLL and an open loop quadrupler. A sub-sampling error extraction (SSEE) technique is introduced to fully detect the deterministic jitter (DJ) in the output clock at much lower speeds with minimal power overhead. An orthogonal 3-path LMS-based adaptation algorithm is …
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Signal generation for millimeter wave and THz applications in InP-DHBT and InP-on-BiCMOS technologies
… frequency is reached by a wideband 328 GHz quadrupler, which delivers -7 dBm output power at 325 GHz and exhibits 0.5 % DC-to-RF efficiency. The final part is devoted to hetero-integrated circuits and the necessary design considerations. Two 250 GHz and 330 GHz sources are demonstrated that …