Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 24 for “"processor architectures"”.
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Elliptic Curve Cryptography on Modern Processor Architectures
… researching efficient implementations on modern processors such as IBM's Cell Broadband Engine and Philip's next generation smart card cores. ECC operations can be thought of as a pyramid of building blocks, from instructions on a core, modular operations on a finite field, point addition & …
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Multipass communication systems for tiled processor architectures
… The characteristics of general-purpose parallel processors for communications processing are explored, as well as the applicability of specific parallel designs to communications processing.
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Software orchestration of instruction level parallelism on tiled processor architectures
… structures at high frequencies. A tiled processor architecture (TPA) eliminates long wires from its design by distributing its resources over a pipelined interconnect. By exposing the spatial distribution of these resources to the compiler, a TPA allows the compiler to optimize for …
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Modeling and evaluation of multi-core multithreading processor architectures in SystemC
Processor design has evolved over the years to take advantage of new technology and innovative concepts in order to improve performance. Diminishing returns for improvements based on current techniques such as exploiting instruction-level parallelism have caused designers to shift their focus. …
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Methodology for VHDL performance model construction and validation
… is emphasized. Typical models of multi-processor architectures are very large and complex. Validation of theses models is difficult and time consuming. This thesis also develops a methodology for model validation. A seventeen processor raceway architecture, that was developed as a part …
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Design of a Multibus Data-Flow Processor Architecture
… best solution. There is a need for specialized processor architectures for specific application areas. This thesis discusses the design of such a specialized processor architecture targeted towards event driven sensor applications. This thesis presents an augmented multibus dataflow processor …
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A Reconfigurable Implementation of Bayesian Phylogenetic Inference
… with the growing demands of biologists. FPGA co-processor architectures have been shown to effectively speed up the performance of software applications by performing the most time-consuming parts of the algorithm on custom hardware. The goal of this thesis is to investigate a reconfigurable …
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Improving performance and security of indirect memory references on speculative execution machines
… hobble efficient and secure execution on current processor architectures. Traditional hardware techniques such as caches and speculative execution are ineffective on demanding workloads, such as in-memory databases, machine learning, and graph analytics. While terabytes of DRAM are now available …
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Scalable memory management using a distributed buddy allocator
The recent rise of multicore processors has forced us to reexamine old computer science problems in a new light. As multicores turn into manycores, we need to visit these problems yet again to find solutions that will work on these drastically different architectures. This thesis presents the …
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TRAPEDS address tracing and its application to multicomputer cache performance analysis
… a difficult problem, particularly for parallel processor architectures. Even when trace capture methods are applicable to parallel processors, the amount of collected data typically grows with the number of processors, thus increasing I/O and tracer storage costs. This thesis presents a new …
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C-Flow : a compiler for statically scheduled message passing in parallel programs
Performance improvement in future microprocessors will rely more on the exploitation of parallelism than increases in clock frequency, leading to more multi-core and tiled processor architectures. Despite continuing research into parallelizing compilers, programming multiple instruction stream …
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Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak
Recent processor architectures such as Intel Westmere (and later) and ARMv8 include instruction-level support for the Advanced Encryption Standard (AES), for the Secure Hashing Standard (SHA-1, SHA2) and for carry-less multiplication. These crypto-instructions are optimized for a single algorithm …
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Securing Software Intellectual Property on Commodity and Legacy Embedded Systems
… secure memory components to complete shifts in processor architectures. While powerful, these approaches often require the development of systems from the ground up or the application of specialized and often expensive hardware components. As a result they are poorly suited to address the …
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A Task-based Programming Methodology Using MCA Standards for Multicore Systems
… heterogeneous systems are here to stay. Thus, processors configured on the same platform may have different instruction-set architectures, different operating systems, and discrete memory space. These features increase the adaptability of the platforms for different applications. However, the …
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Reducing memory persistency overheads with transparent out-of-place updates
… called PIL, along with minor changes to existing processor architectures which together enable efficient transaction execution in hardware. Experimental results with a variety of data structures and data-intensive applications show that PIL achieves low critical-path latency with small write …
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Making Computation on Encrypted Data Practical through Hardware Acceleration of Fully Homomorphic Encryption
… with complex dependencies that current vector processor architectures cannot handle, as well as extreme memory bandwidth demands. This thesis presents two FHE accelerators that address these challenges: F1 and CraterLake. F1 is the őrst programmable FHE accelerator, i.e., capable of executing …
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Power estimation and power optimization policies for processor-based systems
… to reduce and estímate the power consumption in processor-based architectures. This work targets embedded systems, inorder and out-of-order processors, cache hierarchies and MPSoCs. Our approaches are designad to reduce or estimate the power consumption while keeping the performance constraints …
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Transparent spilling and refilling of partitioned overlapping register window register organizations with a remote instruction pointer
Register allocation is critical to processor performance. Registers are the fastest storage system available to a processor. The more capable a register set's organization is at maintaining process context, the fewer the number of memory accesses the processor will need to make. Overlapping …
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TIME-PREDICTABLE FAST MEMORIES: CACHES VS. SCRATCHPAD MEMORIES
In modern processor architectures, caches are widely used to shorten the gap between the processor speed and memory access time. However, caches are time unpredictable, especially the shared L2 cache used by different cores on multicore processors. Thus, it can significantly increase the complexity …
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