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Showing 1 to 1 of 1 for “"power-on electrostatic discharge (ESD)"”.
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Logic upset induced by substrate current during power-on ESD
… we will describe an experimental study of one possible soft failure mechanism during power-on electrostatic discharge (ESD). For contact discharge into a test chip mounted on a board, logic upsets can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ …