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Showing 1 to 3 of 3 for “"power-aware design"”.

  1. Protocol stacks for power-aware wireless microsensor networks

    … exploit these time-varying scenarios to obtain power savings by adjusting its operating conditions accordingly. A coherent design of application-specific network protocol stacks is the key. Specifically, embedding power aware features in the link layer and media access control (MAC) layer …

    mit Repository record for Protocol stacks for power-aware wireless microsensor networks (opens in a new tab)

  2. High Level Power Estimation and Reduction Techniques for Power Aware Hardware Design

    … led to an unprecedented complexity of hardware designs. These factors have necessitated the abstraction level of design-entry of hardware systems to be raised beyond the Register-Transfer-Level (RTL) to Electronic System Level (ESL). However, power envelope on the designs due to packaging and …

    vt Repository record for High Level Power Estimation and Reduction Techniques for Power Aware Hardware Design (opens in a new tab)

  3. Temperature and Interconnect Aware Unified Physical and High Level Synthesis

    … CMOS integrated circuits has created significant design challenges arising from increasing power densities, thermal concerns, and rising wire delays. The main contribution of this dissertation is the development of unified physical and high-level synthesis techniques for the design of ASICs with …

    usf Repository record for Temperature and Interconnect Aware Unified Physical and High Level Synthesis (opens in a new tab)