Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 17 of 17 for “"place and route"”.
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Fast place and route approaches for FPGAs
… of Technology, Dept. of Electrical Engineering and Computer Science, 1999.
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A Genetic Algorithm-Based Place-and-Route Compiler For A Run-time Reconfigurable Computing System
… platform to the specific problem at hand. An experimental computing model known as wormhole run-time reconfiguration allows for partial reconfiguration and is highly scalable. In this approach, configuration information and data are grouped together in a computing unit called a stream, …
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Design and Investigation of Genetic Algorithmic and Reinforcement Learning Approaches to Wire Crossing Reductions for pNML Devices
… in the polarization of single-domain nanomagnets and performs operations via fringing field interactions. Currently, there is no complete top-down workflow for pNML. Researchers must instead simultaneously handle place-and-route, timing, and logic minimization by hand. These tasks include multiple …
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A Standalone Wire Database for Routing and Tracing in Xilinx Virtex, Virtex-E, and Virtex-II FPGAs
… millions of wires. While mainstream design flows and place-and-route tools make very good use of these routing resources, they do so at the cost of very significant processing time. A well established alternative scheme is to modify or generate configuration bitstreams directly, resulting in more …
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Differential Power Analysis In-Practice for Hardware Implementations of the Keccak Sponge Function
… is the winner of the National Institute of Standards and Technology (NIST) competition to develop the Secure Hash Algorithm-3 Standard (SHA-3). Prior work has developed reference implementations of the algorithm and described the structures necessary to harden the algorithm against power …
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Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity
… not kept pace with the increase in design size and FPGA density. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We address the implementation problem using a divide-and-conquer approach. The PATIS automatic floorplanner enables …
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Physical-Security for Wireless with Orbital Angular Momentum Wave
As technology progresses and an ever-increasing number of digital data are transmitted day to day, securing data has emerged as a major field of research. Conventional cryptography in higher layers of protocol stack has been studied as a data protection technique from an unauthorized party by …
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Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity
… density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We approach the problem in a different way for development environments in which some circuit speed and area optimization may be sacrificed for improved implementation …
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A framework for synthesis from VHDL
This thesis describes the design and implementation of a hardware synthesis system based on design descriptions provided in VHDL. Several aspects of the synthesis problem are examined. These include the design of an internal format to represent multiple levels of design information, algorithms for …
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CAD for a 3-dimensional FPGA
… to specify 3-dimensional FPGA architectures and map RTL descriptions of circuits to these 3-D FPGAs. The CAD tool was created from the widely used Versatile Place and Route (VPR) CAD tool for 2-D FPGAs. The tool performs timing-driven placement of logic blocks in the 3-dimensional grid of the …
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Temperature and Interconnect Aware Unified Physical and High Level Synthesis
… increasing power densities, thermal concerns, and rising wire delays. The main contribution of this dissertation is the development of unified physical and high-level synthesis techniques for the design of ASICs with optimal chip temperatures and interconnect delays. Thermal issues are becoming …
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FPGA-based programmable embedded platform for image processing applications
… systems including medical, surveillance and critical infrastructure employs image processing to provide intelligent analysis. They use onboard pre-processing to reduce data bandwidth and memory requirements before sending information to the central system. Field Programmable Gate Arrays …
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The role of attention in spatial (dis)orientation of older adults.
… abilities. These changes are widespread and affect many components of the navigation system. Such changes have profound effects on an individual’s independence as their ability to learn and find their way through novel environments diminishes. Among the widespread age-related changes are …
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Robust and reliable hardware accelerator design through high-level synthesis
… complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard …
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System level simulation of digital designs : a case study
… in South Africa, as it is both a synthesis and simulation language. Many designers make use of the language's synthesis ability but hardly tap into the power of its simulation abilities. This dissertation primarily investigated the feasibility of VHDL simulation during the design process. …
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Tutorial on designing and implementing a direct digital synthesizer (DDS) on a field programmable gate array (FPGA)
… require a fast switching, fine tuning and superior quality sinusoidal signal source for their components. One such a frequency synthesizer is a direct digital synthesizer (DDS). This thesis work utilizes a design that aims to combine digital circuit design and electronic communication …