Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 13 of 13 for “"pipelined ADC"”.
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Precision hybrid pipelined ADC
… but not limited to single-ended and differential pipelined ADCs, with effective number of bits (ENOB) ranging from 8 bits to 11 bits at sampling rates from 10MS/s to 100MS/s. The purpose of this project was to explore the use of the ZCBC technique for high-precision ADCs. The goal of the project …
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Techniques for Reliable and Efficient Analog to Digital Conversion
Analog-to-Digital conversion (ADC) is an essential process in signal processing. It converts analog signals in the real world to digital codes that can be conveniently processed by digital systems. Among various ADC architectures, pipelined ADC is very attractive since it can achieve high …
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Floating-Point Analog-to-Digital Converter
… a floating-point analog-to-digital converter (FP-ADC) has been investigated. This approach de-links the dynamic range with the resolution, and a very wide dynamic range can be achieved by an ADC with a moderate resolution. The solution for an FP-ADC presented in this thesis is to amplify the input …
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High-Resolution Nyquist -Rate Analog -to -Digital Converter
This thesis presents a pipelined analog-to-digital converter (ADC) employing a capacitor error-averaging technique with look-ahead decision and digital error correction concepts that has been implemented in a CMOS technology to achieve high linearity and high speed. The capacitor error-averaging …
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A pipelined analog-to-digital converter with low-gain, low-bandwidth op-amps
Designing a high-gain, high-bandwidth op-amp for pipelined ADCs in fine-line CMOS technology has become increasingly challenging. In order to address this issue, this thesis presents the shadow-ADC-assisted digital calibration technique. The proposed technique relaxes op-amp performance …
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A high performance zero-crossing based pipelined analog-to-digital converter
In this thesis, I describe a zero-crossing based pipelined ADC. Unlike traditional pipelined ADCs, this work does not use any op-amps in the signal path. The use of zero-crossing based circuits made it possible to achieve a much better figure of merit. The ADC is design to operate at 200MS/s with a …
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A reconfigurable analog-to-digital converter for a mobile receiver
… In terms of analog-to-digital converters (ADCs) of mobile terminal receivers, this indicates higher sample rate, lower power consumption and higher resolution. With comparison to other ADCs, the pipelined ADC architecture has most successfiilly covered the wide resolution limits and data …
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Low-Spurious Analog-to-Digital Conversion Using Multi-Stage Code-Error Calibration
This thesis presents a 5-5-5-6b pipelined ADC architecture that alleviates the requirements for initial capacitor matching and residue amplifier settling accuracy. The two 5-bit MSB stages are digitally calibrated to implement a 15-bit, 5 Msample/s low-spurious ADC using 1.4 $\mu$m CMOS. A …
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Virtual ground reference buffer technique in switched-capacitor circuits
… The concept is demonstrated in a 12-b 250MS/s pipelined ADC.
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A comparator-based switched-capacitor pipelined analog-to-digital converter
… the technique is demonstrated in the design of a pipelined analog-to-digital converter. The prototype CBSC 1.5 b/stage pipelined ADC implemented in a 0.18 [mu]m CMOS process operates at 7.9MHz, achieves 8.6 effective bits of accuracy, and consumes 2.5mW of power. Sources of offset and nonlinearity …
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A time-interleaved Zero-Crossing-Based analog-to-digital converter
… The switched capacitor multiplier circuit in pipelined ADC is one application which has been hindered by op-amp limitations. Zero Crossing Based (ZCB) switched-capacitor topologies have been proposed as an alternative to op-amp based circuits because ZCB circuits do not suffer from the same …
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Techniques for low-power high-performance ADCs
Analog-to-digital converters (ADCs) are essential building blocks in many electronic systems which require digital signal processing and storage of analog signals. Traditionally, ADCs are considered a power hungry circuit. This thesis investigates ADC design techniques to achieve high-performance …
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SHA-less pipeline ADC design with sampling clock skew calibration
… of pipeline analog-to-digital converters (ADCs) can be substantially improved by eliminating the front-end sample-and-hold amplifier (SHA). However, in a SHA-less architecture the sampling clock skew between the sub-ADC and the multiplying digital-to-analog converter (MDAC) in the pipeline …