Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 187 for “"phase locked"”.
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A phase-locked loop for laser scanners
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1984.
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Phase Noise in CMOS Phase-Locked Loop Circuits
Phase-locked loops (PLLs) have been widely used in mixed-signal integrated circuits. With the continuously increasing demand of market for high speed, low noise devices, PLLs are playing a more important role in communications. In this dissertation, phase noise and jitter performances are …
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Phase-locked loop using time-based integral control
… the time-based techniques in the context of phase-locked loop (PLL) implementation. Many studies of the topic have been performed in the past. Functioning as an effective replacement of passive capacitors, time-based integrators using oscillators prove to be more area efficient and highly …
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An optical phase locked loop for semiconductor lasers
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics, 1988.
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A digital phase-locked ultrastable wideband FM oscillator.
Thesis: M.S., Massachusetts Institute of Technology, Department of Electrical Engineering, 1970
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Real-time spatial-phase-locked electron-beam lithography
… often worse than its resolution. Spatial-phase-locked electron-Beam lithography (SPLEBL) improves the placement accuracy of EBL tools to the nanometer level by directly referencing the beam position via a global-fiducial grid placed on the substrate, and providing feedback corrections to …
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Optical excitation of bulk semiconductors by phase-locked pulses.
Optical excitation of bulk semiconductors by phase-locked pulses.
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FPGA-based digital phase-locked loop analysis and implementation
The thesis presents a digital PLL project that will be used as an ECE 463 lab module and serve as a platform for future communication research projects. Field Programmable Gate Array (FPGA) technology is used for all digital signal processing tasks. A Direct Digital Synthesizer (DDS) is used to …
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Low-voltage spatial-phase-locked scanning-electron-beam lithography
Spatial-phase-locked electron-beam lithography (SPLEBL) is a method that tracks and corrects the position of an electron-beam in real-time by using a reference grid placed above the electron-beam resist. In this thesis, the feasibility of spatial-phase-locked lowvoltage electron-beam lithography is …
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Phase-locked loop digital FM receiver for wireless communications
Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.
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Analysis and design of high order digital phase locked loops
The Phase Locked Loop (PLL) is an important component of many electronic devices; it can be employed as a frequency synthesizer, for clock data recovery, and as amplitude and frequency demodulators. It is an inherently nonlinear closed loop feedback system; the nonlinearity is due mainly to the …
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Clock synthesizer design with analog and digital phase locked loop
… clocking circuit used in high-speed links is the Phase-Locked Loop (PLL). This thesis provides an in-depth analysis of basic analog PLL theory, architecture and transistor level design. The all-digital counterpart of the analog PLL will also be presented for its ultra low power and small …
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A 1.6-3.2GHz, high phase accuracy quadrature phase locked loop
… quadrature outputs, and is geared towards low phase noise. The VCO is identified as the limiting factor in the tuning range and source of the quadrature outputs, as well as the primary source of the phase noise above the loop bandwidth of the PLL, so its design is the principle focus herein. …
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Feasibility study of spatial-phase-locked focused-ion-beam lithography
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 1995.
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A Novel Passive Islanding Detection Method Based on Phase-Locked Loop
… existing passive IDMs, and an analysis of the phase-locked loop (PLL) behaviour under grid-connected and islanded conditions using its quasi-static model. Based on the results of these studies, a novel passive IDM is developed that utilizes the PLL error to detect islanding with a small NDZ and …
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Low jitter phase-locked loop clock synthesis with wide locking range
… integration in many communications applications. Phase noise and timing jitter are important design considerations for these communications applications. The desire for highly complex levels of integration using low cost CMOS technologies works against the minimization of timing jitter and phase …
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A new programmable low noise all digital phase-locked loop architecture
… today almost without exception there are phase-locked loops (PLL) implemented within each system and often within each integrated circuit (IC). In fact, most PLL's are implemented monolithically within ICs without any or with very few external components. Additionally, most are implemented …
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Dissertation review on a new control perspective on phase locked loops
The technique of phase-locked loop (PLL), an essential means for online frequency detection of incoming signal, which is widely used in our modern day communication system. PLL is traditionally viewed as a non-linear feedback control loop that will automatically locks the adjustable frequency of a …
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Design of all digital phase-locked loop in serial link communication
… speed links, clocking circuitry is vital, and phase-locked loop (PLL) is at the heart of every on-chip clocking circuit. The clocking circuitry needs to be robust, low-power and fast in order to fulfill the increasing demand for high data rate links. The performance of the input/output (I/O) …
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