Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 37 for “"path delay"”.
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SCALABLE TEST GENERATION FOR PATH DELAY FAULTS
… design has drawn a lot of attention towards the path delay fault model (PDF) [1], which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes [2]. Path …
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Search-space Aware Learning Techniques for Unbounded Model Checking and Path Delay Testing
… and Testing: Unbounded Model Checking and Path Delay Fault Testing, that commonly suffer from extremely large memory requirements. We propose efficient representations and intelligent learning techniques that reason on the problem structure and take advantage of the repeated search space, …
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Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests
… of digital integrated circuits increase rapidly, delay testing is indispensable to guarantee the correct timing behavior of the circuits. In this dissertation, we describe methods developed for three aspects of delay testing in scan-based circuits: test generation, path selection and built-in test …
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Timing Driven Analytical Placement for FPGA
… best results in terms of wirelength and critical path delay. The runtime for these SA based methods is directly proportional to the total number of cells to be placed. In case of modern multi-million gate FPGAs, SA based methods for placement dominate the total runtime in the FPGA CAD flow. In …
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High Quality Transition and Small Delay Fault ATPG
Path selection and generating tests for small delay faults is an important issue in the delay fault area. A novel technique for generating effective vectors for delay defects is the first issue that we have presented in the thesis. The test set achieves high path delay fault coverage to capture …
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Static Learning for Problems in VLSI Test and Verification
… we define a new concept called multi-cycle path delay faults (M-pdf) for latch based designs with multiple clock domains, and propose an implications-based methodology for the identification of untestable M-pdfs for such designs. One of the main bottlenecks in the efficiency of …
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A combined clustering and placement algorithm for FPGAs
… the proposed algorithm achieves an 11\% critical-path delay improvement compared to the VPR academic tool flow. This performance improvement is obtained at the expense of a 44\% increase in area usage and a 26x increase in maximum runtime. Techniques have also been implemented to sacrifice …
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PARALLEL DELAY FAULT GRADING HEURISTIC AND TESTING APPROACHES TO TROJAN IC DETECTION
A method to perform implicit path delay fault grading on GPGPU architectures is presented. Experimentally it is shown that it is over 1200x faster than a single-core implicit path delay fault grading method previously in the literature for higher accuracy and can be shown to scale to multiple …
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Optimization Techniques for Performance and Power Dissipation in Test and Validation
… the sensitization characteristics of a path to be tested. The path delay fault models have been used for the purpose of studying this problem. Another important aspect in chip design is performance validation, which is increasingly perceived as the major bottleneck in integrated circuit …
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Reliable and Low -Power Signal Processing via Algorithmic Noise -Tolerance
… reduced beyond the limit imposed by the critical path delay to reduce energy dissipation. The resulting degradation in algorithmic performance is restored by employing ANT, thereby achieving energy savings while meeting the algorithmic performance specifications.
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Behavioral delay fault modeling and test generation
… of operation of VLSI devices has increased, delay fault testing has become a more important factor in VLSI testing. Due to the large number of gates in a VLSI circuit, the gate level test generation methodologies may become infeasible for delay test generation. In this work, a new behavioral …
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A truly embedded test structure for design-for-manufacturability, hardware security and VLSI testing
… significant. Moreover, the process variations in path delays are increasingly dependent on circuit context. Given this 'neighborhood' dependence, characterization of path delays is best carried out using embedded techniques applied to actual product macros, as opposed to scribe line test …
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Arithmetic data value speculation.
… an arithmetic circuit by shortening the critical path delay or the sampling period so that result is not guaranteed to be correct for every input combination.Thus, an acceptable compromise between the circuit latency and the average probability of correctness drives the circuit design. Two methods …
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DETECTING DELAY ANOMALIES INTRODUCED BY HARDWARE TROJANS USING CHIP AVERAGING AND AN ON-CHIP HIGH RESOLUTION EMBEDDED TEST STRUCTURE
… and detecting small systematic changes in path delays introduced by capacitive loading effects or series inserted gates of HTs. The path delays are measured using a high resolution on-chip embedded test structure called a time-to-digital converter (TDC) that provides approx. 25 ps of timing …
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Control and detection of complex fields in spatio-temporal optical systems
… errors that cause uncertainties in the path delay between interfering beams. Experimental results that demonstrate the detection of complex space-time fields are presented. Holographic pulse-shaping techniques for recording information on ultra-fast space-time fields are analyzed. …
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The Polarimetric Impulse Response and Convolutional Model for the Remote Sensing of Layered Vegetation
… for arbitrary pulse waveforms through simple path delay method. These techniques lend physical insight into the actual scattering mechanisms behind the returned waveform, as well as offer explanations for why approximations of previous authors' break down in certain regions. Furthermore, these …
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Transceiver design and system optimization for ultra-wideband communications
… based on an accurate frequency-dependent path loss calculation to account for variations across the ultra-wide bandwidth of the signal. Achievable information rates are quantified as a function of transmission distance over additive white Gaussian noise and multipath channels under …
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Exploiting irregular parallelism to accelerate FPGA routing
… often with a target of minimizing critical path delay. This optimization problem is known to be NP-hard, and existing algorithms for approximating it exhibit very little regular parallelism. This thesis accelerates the routing phase of VTR 8.0, a commonly used, open-source research tool for …
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Reducing synchronization in distributed parallel programs
… include communication latency, critical path delay, suboptimal scheduling, load imbalance, and system noise. These challenges are often defined and measured relative to points of broad synchronization in the program’s execution. Given the way in which many algorithms are defined and …
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Performance-driven chip floorplanning and global routing
… VLSI design are presented. Interconnection delays are estimated and directly incorporated into the problem formulations. A timing analysis provides timing information consisting of a set of potentially critical paths and the delay slacks of the signal nets. This information is used to …
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