Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 26 for “"partial reconfiguration"”.
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Educational applications of partial reconfiguration of FPGAS
The use of partial reconfiguration (PR) in reconfigurable systems such as Field Programming Gate Arrays (FPGAs) has gained a lot of attention during the past ten years. Recently, Xilinx has released the first commercially available PR implementation for its FPGAs. However, there is a lack of …
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High-speed dynamic partial reconfiguration for field programmable gate arrays
With dynamically and partially reconfigurable designs, it is necessary that the speed of the reconfiguration be accomplished in a time that is sufficiently small such that the operation of reconfiguration is not the limiting factor in the process. Therefore, the communication between the source of …
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OpenPR: An Open-Source Partial Reconfiguration Tool-Kit for Xilinx FPGAs
The Xilinx Partial Reconfiguration tool kits have been instrumental for performing a wide variety of research on Xilinx FPGAs. These tool kits provide a methodology for creating rectangular partial reconfiguration modules that can be swapped in and out of a static baseline design with one or more …
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An embedded system supporting dynamic partial reconfiguration of hardware resources for morphological image processing
… a unique capability of FPGAs called dynamic partial reconfiguration (DPR) which allows changing the hardware configuration of silicon pieces at runtime. DPR allows regions of the FPGA to be reprogrammed with new functionality while applications are still running in the remainder of the …
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BitMaT - Bitstream Manipulation Tool for Xilinx FPGAs
With the introduction of partially reconfigurable FPGAs, we are now able to perform dynamic changes to hardware running on an FPGA without halting the operation of the design. Module based partial reconfiguration allows the hardware designer to create multiple hardware modules that perform …
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Design and Implementation of an FPGA-based Partially Reconfigurable Network Controller
… that cannot be integrated into ASICs is runtime reconfiguration in which, certain portions of the chip are reconfigured at runtime while the other parts continue to operate normally. This feature is required for network controllers with multiple data transfer channels that need to preserve the …
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A Physical Layer Implementation of Reconfigurable Radio
… a suitable platform to achieve such run-time reconfigurations of the physical layer of the radio. This thesis explores the use of FPGAs in the design of reconfigurable radios. The results presented here demonstrate how FPGAs can be used to provide the flexibility, performance, efficiency and …
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A timeshared, runtime reconfigurable hardware co-processing architecture
… thesis, we explore the potential of using FPGA partial reconfiguration to create a platform for customized hardware cores that may be loaded on demand, at runtime, and replaced when not in use. We implement two new software tools, bitparse and bitrender, to demonstrate the bitstream relocation …
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Dynamic Module Library Generation for FPGA-based Run-Time Reconfigurable Systems
… entire run-time reconfigurable systems using partial reconfiguration. Module-based run-time reconfiguration permits the construction of custom applications at run-time using pre-compiled Intellectual Property (IP) from a module library. The need for both flexible module placement and custom …
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Structured Approach to Dynamic Computing Application Development
… projects and a decade of research, the dynamic reconfiguration of Field Programmable Gate Arrays (FPGAs) is still very much an art practiced by few. Previous attempts to automate the many low-level details that complicate Run-Time Reconfigurable (RTR) application development suffer severe …
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Framework for Hardware Agility on FPGAs
… universities has successfully developed run-time reconfiguration tools to make FPGA designs more flexible and thus vastly reducing configuration times. Developers now have a more powerful platform with dense Digital Signal Processor resources and the flexibility of SDR. Xilinx offers tools such as …
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Reconfigurable and heterogeneous architectures for efficient computing
… this dissertation explores the use of reconfiguration to balance flexibility, performance, and energy efficiency. We begin by presenting three novel approaches that explore the use of reconfiguration in the three dominant computing devices -- CPUs, GPUs, and FPGAs. First, we consider …
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A Genetic Algorithm-Based Place-and-Route Compiler For A Run-time Reconfigurable Computing System
… computing model known as wormhole run-time reconfiguration allows for partial reconfiguration and is highly scalable. In this approach, configuration information and data are grouped together in a computing unit called a stream, which can tunnel through the chip creating a series of …
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Module Shaping and Exploration in Rapid FPGA Design and Assembly Workflows
… design including Hierarchical Design Flow and Partial Reconfiguration Flow, OpenPR, HMFlow, PARBIT, REPLICA, GoAhead and QFlow frameworks. As all of these projects have shown, a modular approach raises the abstraction level, provides clear boundaries for incremental design, reduces placement …
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Dynamically reconfigurable management of energy, performance, and accuracy applied to digital signal, image, and video Processing Applications
… The systems are then demonstrated using Dynamic Partial Reconfiguration (DPR) and dynamic frequency control on FPGAs. The framework is demonstrated on: i) a dynamic pixel processor, ii) a dynamically reconfigurable 1-D digital filtering architecture, and iii) a dynamically reconfigurable 2-D …
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Dynamic reconfiguration methods in FPGA-based softawre defined radio system for wireless mobile standards
… SDR systems based on FPGAs can suffer from long reconfiguration overhead, high resource utilisation requirements, high power consumption, and inflexible standards switching. With the conversion from analogue to digital television, a large amount of licensed spectrum is being released, and this is …
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FPGA structures for high speed and low overhead dynamic circuit specialization
… interface. However, modern techniques such as Partial Reconfiguration (PR) enable us to configure a part in the configuration memory with partial bitstreams during run-time. The reconfiguration is achieved by swapping in partial bitstreams into the configuration memory via a configuration …
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Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs
FPGA design implementation and debug tools have not kept pace with the advances in FPGA device density. The emphasis on area optimization and circuit speed has resulted in longer runtimes of the implementation tools. We address the implementation problem using a divide-and-conquer approach in which …
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Dynamically Reconfigurable Architectures and Systems for Time-varying Image Constraints (DRASTIC) for Image and Video Compression
… over power consumption. The use of dynamic partial reconfiguration with Field Programmable Gate Arrays (FPGAs) provides an opportunity to effectively control dynamic power consumption by jointly considering software-hardware configurations. This dissertation extends traditional …
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PicoRF: A PC-based SDR Platform using a High Performance PCIe Plug-in Card Extension
… run-time. Through a high speed PCIe connection, partial bitstreams can be downloaded from the host PC to the FPGA at a very high speed making it possible for the radio to modify its function in very short time intervals and greatly reducing the service interruption time. Control software running …
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