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Showing 1 to 11 of 11 for “"parasitic resistances"”.

  1. Modeling and control of three-phase PWM converters

    … the voltage sources or capacitors with nonzero parasitic resistances are placed across the converter dc port or ac terminals. The effects of the parasitic resistances are described by additional time-varying terms in the average models depending not only on the duty cycle values, but also on the …

    vt Repository record for Modeling and control of three-phase PWM converters (opens in a new tab)

  2. Process Development for High Speed Transistor Laser Operation

    … recombination lifetime; it is also limited by parasitic resistances and capacitances. Small signal bandwidth of 20 GHz and digital modulation of 20 Gbit/s was obtained by reducing or eliminating extrinsic parasitics which limit device performance through the optimization of device geometry and …

    uiuc Repository record for Process Development for High Speed Transistor Laser Operation (opens in a new tab)

  3. An electrically driven 8-14µm band solid-state modulator

    … current flow through its electrodes due to parasitic resistances, the use of current mirrors is proposed to force current through different regions of the electrode to improve its performance.

    soton Repository record for An electrically driven 8-14µm band solid-state modulator (opens in a new tab)

  4. A flexible underwater pressure sensor array for artificial lateral line applications

    … dissipated by the amplification circuitry and parasitic resistances. Each sensor is capable of transducing up to a 1 kPa pressure differential across its diaphragm, though the sensor may respond to signals of this amplitude at arbitrary underwater depth due to the use of a pressure …

    mit Repository record for A flexible underwater pressure sensor array for artificial lateral line applications (opens in a new tab)

  5. Predictive transient circuit simulations of charged device model ESD events in system in package chips

    … A method to model the on-die circuits and parasitic resistances of the power/ground busses is also presented. The circuit simulations were used to (a) study domain crossing circuits in single and multi-die packages, (b) study inter-die interface circuits in the stacked die and 3D integrated …

    uiuc Repository record for Predictive transient circuit simulations of charged device model ESD events in system in package chips (opens in a new tab)

  6. Optimal MOSFET design for low temperature operation

    … saturation velocity. Equally as important, the parasitic resistances of the device and of the interconnect decrease as temperature decreases. The approach of this thesis is to use comparisons of optimal designs across channel lengths and across temperatures to accurately assess the performance …

    mit Repository record for Optimal MOSFET design for low temperature operation (opens in a new tab)

  7. An Exploration of Entropy Sources in Standard CMOS for Cryptographic Applications

    … quantum tunnelling as a tool to extract series parasitic resistances is proposed and demonstrated, where by an analytical augmented model is able directly estimate the resistance value through either an analytical solution or parameter estimation techniques. This is verified with scattering …

    unsw Repository record for An Exploration of Entropy Sources in Standard CMOS for Cryptographic Applications (opens in a new tab)

  8. Performance limits of RF power CMOS

    … through careful device layout for minimized parasitic resistances and capacitances. Total output power approaching 70 mW was measured on 45 nm CMOS devices by increasing the device width to 640 gm. However, we find that the output power scales non-ideally with device width because of an …

    mit Repository record for Performance limits of RF power CMOS (opens in a new tab)

  9. Packaging of Enhancement-Mode Gallium Nitride High-Electron-Mobility Transistors for High Power Density Applications

    … to their Si-based counterparts. Minimizing the parasitic loop inductances of the GaN HEMT package is crucial for reducing electromagnetic interference (EMI) noise and voltage spikes. Another concern with GaN HEMTs comes from their lower thermal conductivity and smaller die size. The HEMTs …

    vt Repository record for Packaging of Enhancement-Mode Gallium Nitride High-Electron-Mobility Transistors for High Power Density Applications (opens in a new tab)

  10. A Power Constrained 433-MHz Low Noise Amplifier

    <p>Within wireless communication systems, low noise amplifiers are critical for the performance of receivers. They are primarily responsible for providing enough gain while adding little noise to overcome the noise of the subsequent stages. The LNA presented here is part of a battery-powered …

    arkansas Repository record for A Power Constrained 433-MHz Low Noise Amplifier (opens in a new tab)

  11. Nuevos procedimientos de análisis de los datos corriente-tensión de iluminación y de oscuridad para la caracterización de células solares

    … one or two exponentials, with and without parasitic resistances, and with fixed or variable ideality diode coefficients. In Chapter 2 we present least squares fitting, applied in our case to the minimization of the distance between the experimental characteristic IV and the calculated curve …

    upm Repository record for Nuevos procedimientos de análisis de los datos corriente-tensión de iluminación y de oscuridad para la caracterización de células solares (opens in a new tab)