Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 22 for “"parasitic capacitances"”.
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Electric field engineering in GaN high electron mobility transistors
… the channel of the device without introducing parasitic capacitances. By reducing the peak electric field, the average electron velocity is increased by 50%. This new technology has the potential to improve not only the cutoff frequencies, but also the breakdown voltage of GaN transistors. To …
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CMOS fingerprint sensor electrostatic modeling
… capacitive imaging process through reduction of parasitic capacitances and sensor cell scaling for future generation devices. Evaluation of sensor cell and array geometries was completed using a commercial 2-D electrostatic field solver. The modeling activities performed include analysis of …
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Noise Optimization for High-Bandwidth Ion Channel Recordings
… ratios can be achieved by minimizing all parasitic capacitances associated with these measurements. A custom integrated amplifier in a 0.13-micron complementary metal oxide semiconductor (CMOS) process is designed for high-bandwidth ion channel recordings, and systems are designed to …
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RF to Millimeter-wave Linear Power Amplifiers in Nanoscale CMOS SOI Technology
… gate oxide breakdown, stability, effect of parasitic capacitances on the performance of the PA and large chip areas have also been addressed. Fully-integrated RF to mm-wave frequency CMOS SOI PAs are successfully implemented and measured using the proposed topology.</p>
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Design of a Phi-2 and a Class E inverter for underwater systems
… Inverter, a topology that uses the inherent parasitic capacitances to substitute for physical components. The WPT system utilizes magnetic resonance coupling to transmit power from transmitter coils attached to the inverters to receiver coils attached to a load through a rectifier. …
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High-Efficiency and High-Power Density DC-DC Power Conversion Using Wide Bandgap Devices for Modular Photovoltaic Applications
… findings on circuit design techniques to reduce parasitic effects. The parasitic inductances induced from PCB layout of primary side circuit can cause the unbalanced resonant current between positive and negative half cycles if the power loops of two half cycles have asymmetrical parasitic …
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High Temperature Characterization and Analysis of Silicon Carbide (SiC) Power Semiconductor Transistors
… current gain, specific on-resistance, parasitic capacitances, internal gate resistance, and the turn on and turn off switching times and energies. For the latter, the driving method used for each device is described in detail. Furthermore, for the devices that require on-state dc …
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Behavioral Modelling of the Transient and CdV/dt Induced Turn-on of a Hybrid High Power Switch Unit
… gate voltage of the low side Si IGBT through the parasitic capacitances. This behavior poses a serious risk of lowering efficiencies in operation as well as safety concerns. In this study, a set of behavior models were developed for both the SiC MOSFET and Si IGBT, with the specific target of …
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Asynchrobatic logic for low-power VLSI design
… and secondly a front-end only (without parasitic capacitances, resistances) simulation that demonstrates a functional system capable of calculating the Greatest Common Denominator (GCD) of a pair of 16-bit unsigned integers, which under typical conditions on a 0.35μm process, executed a …
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Improvement of carbon nanotube-based field-effect transistors by cleaning and passivation
… barrier is expanded by the reduction of parasitic capacitances in the transistor. In this context, two so far barely considered materials, hydrogen silsesquioxane and Xdi-dcs, a polymer mixture of poly(vinylphenol) and polymethylsilsesquioxane, are investigated and assessed. The novelty …
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Monolithic finite gain amplifiers employing active voltage attenuators in the feedback and a charge conserving macromodel for MOSFETs
… Based on the review and the nature of the parasitic capacitances in the MOSFET, a charge conserving macromodel is developed. This macromodel provides a convenient and accurate means for simulating the non-ideal effects of charge injection of MOSFET switches. A simple sample-and-hold circuit …
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A surface-potential-based compact model for partially-depleted silicon-on-insulator MOSFETs
… competitive compared to bulk, due to their lower parasitic capacitances and leakage currents. The shift towards high frequency, low power circuitry, coupled with the increased maturity of SOI process technologies, have made SOI a genuinely cost-effective solution for leading edge applications. …
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Vertical InAs Nanowire Devices and RF Circuits
… as close to intrinsic operation as possible, parasitic capacitances and resistances in the device structure need to be minimised. A novel self-aligned gate-last fabrication method for vertical InAs nanowire transistors has been developed, that allows for an optimum design of the channel and …
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A new inverse-modeling-based technique for sub-100-nm MOSFET characterization
… very short channel-lengths, (3) is immune to parasitic capacitances and noise, (4) has low sensitivity to gate area variations, (5) has low dependence on mobility, (6) is non-destructive, and (7) uses easily obtainable data. A second goal of the thesis is to demonstrate that knowledge of the …
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Switching-Loss Measurement of Current and Advanced Switching Devices for Medium-Power Systems
… This is mainly due to the fact that the parasitic reactive elements are nonlinear and not as readily documented as I-V characteristics of a given power device. For example, non-linear parasitic capacitances in the device are given for a fixed frequency across a voltage sweep. Parasitic …
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Design of Integrated, Low Power, Radio Receivers in BiCMOS Technologies
… designed to resonate with both intentional and parasitic capacitances, forming stable tuned circuits operating from 100 MHz to over 1 GHz. Although the Q of the inductors employed is typically small (Q < 10), negative resistance circuits can be used to increase the effective Q to arbitrarily …
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Gallium nitride high electron mobility transistors in chip scale packaging: evaluation of performance in radio frequency power amplifiers and thermomechanical reliability characterization
… chip scale packages, and with inherently low parasitic capacitances and inductances. In this work, two types of inexpensive commercially available AlGaN/GaN high electron mobility transistors (HEMTs) in chip scale packages are evaluated in a set of three interconnected experiments. The first …
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GaN heterojunction FET device Fabrication, Characterization and Modeling
… method has been developed, in which the parasitic capacitances were attained from the cold pinch-off measurements while the rest of the parameters from the optimization routine. Small simulation error can be achieved by this method over various bias conditions, demonstrating its …
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On Hardware Implementation of Discrete-Time Cellular Neural Networks
… technology but was small and suffered from parasitic capacitances and resistances leading to undesired behaviour. Later implementations focus on larger network and higher level of robustness. Mixed full-custom chips are most famous and widely considered as a roadmap for advanced …
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DESIGN OF DYNAMIC CAPACITIVE WIRELESS POWER TRANSFER SYSTEMS FOR ELECTRIC VEHICLE CHARGING
… charging pads that minimizes the effect of parasitic capacitances present in the charging environment while maintaining a favorable cost-performance tradeoff. Furthermore, a novel technique using metasurface-based coupling plates (referred to as ‘metacoupler’) to reduce the fringing …
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