Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 16 of 16 for “"on-chip networks"”.
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On-chip networks for manycore architecture
… the past decade, increasing the number of cores on a single processor has successfully enabled continued improvements of computer performance. Further scaling these designs to tens and hundreds of cores, however, still presents a number of hard problems, such as scalability, power efficiency and …
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Fine-grained Adaptivity for Dynamic On-chip Networks
A key challenge of building chip multiprocessors (CMPs) is providing an efficient communication infrastructure for their increasing communication demands. Networks-on-Chip (NoCs) offer a scalable, high-bandwidth, low-latency solution to this problem, but unfortunately incur significant area and …
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Low-swing signaling for energy efficient on-chip networks
On-chip networks have emerged as a scalable and high-bandwidth communication fabric in many-core processor chips. However, the energy consumption of these networks is becoming comparable to that of computation cores, making further scaling of core counts difficult. This thesis makes several …
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Design and implementation of low-latency, low-power reconfigurable on-chip networks
In this dissertation, I tackle large, low-latency, low-power on-chip networks. I focus on two key challenges in the realization of such NoCs in practice: (1) the development of NoC design toolchains that can ease and automate the design of large-scale NoCs, paving the way for advanced …
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Static and dynamic virtual channel allocation for high performance, in-order communication in on-chip networks
Most routers in on-chip interconnection networks (OCINs) have multiple virtual channels (VCs) to mitigate the effects of head-of-line blocking. Multiple VCs necessitate VC allocation schemes since packets or flows must compete for channels when there are more flows than virtual channels at a link. …
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Fuzzy-token: An adaptive Mac protocol for wireless network-on-chip
… than a thousand processor cores within a single chip. In this context, as parallel programs continue to increase the amount of data sharing and signaling between cores, on-chip communication becomes a critical issue. Unfortunately, traditional on-chip networks have been proven to not scale well …
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HAsim : cycle-accurate multicore performance models on FPGAs
… modeling of multicore processors using FPGAs. Contributions include a distributed technique controlling simulation on a highly-parallel substrate, hardware design techniques to reduce development effort, and a specific framework for modeling shared-memory multicore processors paired with …
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Improving Multicore Resource Efficiency and Performance
… towards shared memory parallel programming to continue enhancing performance. Shared memory parallel programming; however is significantly more challenging than its sequential counterpart. Conventional shared memory parallel programs can fall victim to deadlocks, livelocks and data races which …
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Efficient and Verifiable Timing Channel Protection for Multi-Core Processors
… vulnerable to timing channel attacks that leak confidential information through the timing of microarchitectural events. Many timing channel attacks are caused by the interference between different programs in the shared resources of a multi-core processor. For example, an attacker program's …
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Reverse Engineering the Intel Cascade Lake Mesh Interconnect
… processors have driven the move to more scalable on-chip networks to allow for efficient communication between the cores, memory subsystem, and other processor peripherals. Intel’s latest line of Scalable processors introduced the mesh interconnect in the form of a two-dimensional network of rings …
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Globally Synchronized Frames for guaranteed Quality-of-Service in shared memory systems
Resource contention among concurrent threads on multicore platforms results in greater performance variability of individual threads than traditionally seen with time-multiplexed threads on single-core platforms. This performance variability makes it hard to provide performance guarantees, degrades …
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Mitigating the Cost, Performance, and Power Overheads Induced by Load Variations in Multicore Cloud Servers
<p>Load variations whether in space or time pose a significant challenge to system designers. These load variations may induce inefficiencies such as load imbalance and over-provisioning, resulting in performance/power/cost overheads. The goal of my research is to mitigate such variation-induced …
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Enabling dedicated single-cycle connections over a shared network-on-chip
Adding multiple processing cores on the same chip has become the de facto design choice as we continue extracting more and more performance/watt from our chips in every technology generation. In this context, the interconnect fabric connecting the cores starts gaining paramount importance. A high …
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Mitigating Memory Controller Side Channels
… timing side channels, where attackers utilize contention within DRAM controllers to infer a victim’s secrets, pose an important challenge to secure computation in shared memory environments. Attacks utilizing these side channels are broad and highly effective, as memory controllers offer a …
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SC²EPTON : high-performance and scalable, low-power and intelligent, ordered Mesh on-chip network
… to multicore processors, to the point where the on-chip interconnect plays a larger role in achieving the desired performance and power goals. Shared memory multicores are subject to data sharing concerns as each processor computes on data locally, and needs to be aware of accesses by other …
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Methodologies, Architectures, and Prototypes for Scaling On- and Off-Chip Interconnects
… to embrace parallelism, both within single chips and across multiple compute devices, in order to meet the growing computational demands. Efficient data movement, both on-chip and off-chip, has thus become increasingly critical. However, scaling on- and off-chip interconnects each presents …