Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 15 of 15 for “"networks-on-chip"”.
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Energy consumption in networks on chip : efficiency and scaling
… is increased by replicating processing cores on a chip rather than making CPUs larger and faster. This design strategy is motivated by the superior energy efficiency of the multi-core architecture compared to the traditional monolithic CPU. If the trend continues as expected, the number of …
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Architectures and Design Automation for Photonic Networks On Chip
Chip-scale photonics has emerged as an exciting field which can potentially solve many of the problems plaguing the high-performance computing industry, from large-scale to embedded. In theory, photonics is a superior communication medium because of its higher bandwidth density using wave-division …
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Towards low-power yet high-performance networks-on-chip
A network-on-chip (NoC), the de-facto communication backbone in manycore processors, consumes a significant portion of total chip power, competing against the computation cores for the limited power and thermal budget. On the other hand, overall system performance of manycore chips increasingly …
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Systematically controlling the error rates in variation-prone networks-on-chip for energy efficiency
Networks-on-Chip (NoCs) are prone to within-die process variation as they span the whole chip. To tolerate variation, their voltages (Vdd) carry overprovisioned guardbands. As a result, prior work has proposed to save energy by dynamically managing Vdd, operating at reduced Vdd while occasionally …
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Carbon nanotubes as interconnect for next generation network on chip
… with their single-core equivalent. Recently, Networks-on-Chip (NoC) have emerged as a communication methodology for multi core chips. Network-on-Chip uses packet based communication for establishing a communication path between multiple cores connected via interconnects. Clock frequency, …
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Network-on-chip design for a chiplet-based waferscale processor
… learning and big data analysis, processors continue to increase in area and incorporate more computational cores. This growth requires innovation in manufacturing processes to build larger systems, and architectural changes to enable performance to scale acceptably. One significant …
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Linear and non linear coupling effects in sequence of microresonators
… integrated devices for signal routing in optical networks on chip. Several type of optical microresonators, both in a single and coupled configuration (CROW, SCISSOR), are discussed starting from the fundamental theory till dealing with novel configurations. The coupling between a Mach-Zehnder …
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Design and Performance Evaluation of Network-on-Chip Communication Protocols and Architectures
… down of transistor technology allows microelectronics manufacturers such as Intel and IBM to build always more sophisticated systems on a single microchip. The classical interconnection solutions based on shared buses or direct connections between the modules of the chip are becoming obsolete as …
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Resource efficient communication in network-based reconfigurable on-chip systems
The constantly growing capacity of reconfigurable devices allows simultaneous execution of complex applications on those devices. The mere diversity of applications deems it impossible to design an interconnection network matching the requirements of every possible application perfectly, leading to …
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Fine-grained Adaptivity for Dynamic On-chip Networks
A key challenge of building chip multiprocessors (CMPs) is providing an efficient communication infrastructure for their increasing communication demands. Networks-on-Chip (NoCs) offer a scalable, high-bandwidth, low-latency solution to this problem, but unfortunately incur significant area and …
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Low Power Techniques for Future Network-on-Chip Architectures
In a multi-many/core system, the Network-on-Chip (NoC) based communication backbone is responsible for a relevant fraction of the overall energy budget. In fact, the I/O buffers, the crossbars of the routers and the inter-router links are the main contributors of the NoC s energy dissipation. …
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Silicon Photonics for All-Optical Processing and High-Bandwidth-Density Interconnects
Silicon photonics has emerged in recent years as one of the leading technologies poised to enable penetration of optical communications deeper and more intimately into computing systems than ever before. The integration potential of power efficient WDM links at the first level package or even …
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Energy scalability of on-chip interconnection networks
On-chip interconnection networks (OCN) such as point-to-point networks and buses form the communication backbone in multiprocessor systems-on-a-chip, multicore processors, and tiled processors. OCNs consume significant portions of a chip's energy budget, so their energy analysis early in the design …
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Low-swing signaling for energy efficient on-chip networks
On-chip networks have emerged as a scalable and high-bandwidth communication fabric in many-core processor chips. However, the energy consumption of these networks is becoming comparable to that of computation cores, making further scaling of core counts difficult. This thesis makes several …