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Showing 1 to 3 of 3 for “"multi-clock"”.

  1. Novel CAD Techniques for New Challenges in Deep Sub-Micron VLSI Design

    … as Configurable Logic Blocks ( CLB), RAMs and multipliers. In Chapter 4, we present an efficient and effective method to reduce circuit leakage power consumption using input vector control. Our algorithm is able to solve the IVC and gate replacement problems simultaneously. A dynamic …

    uiuc Repository record for Novel CAD Techniques for New Challenges in Deep Sub-Micron VLSI Design (opens in a new tab)

  2. Timing Analysis and Behavioral Synthesis with Process Variation

    … to handle complicated timing constraints such as multi-clock domain circuits, false paths, and multi-cycle paths. The second piece of work extends the behavioral synthesis task of binding to be variation-aware through our algorithm FastYield. FastYield off ers several contributions to the field of …

    uiuc Repository record for Timing Analysis and Behavioral Synthesis with Process Variation (opens in a new tab)

  3. Formal Model Driven Software Synthesis for Embedded Systems

    … interval between ticks of an external reference clock. Since this external reference tick was unrelated to variables (or signals) within the software, redundant operations such as reading of ports, computation of guards were performed for each tick. In this dissertation, we highlight some of …

    vt Repository record for Formal Model Driven Software Synthesis for Embedded Systems (opens in a new tab)