Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 97 for “"memory management"”.
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Intelligent Memory Management Heuristics
Automatic memory management is crucial in implementation of runtime systems even though it induces a significant computational overhead. In this thesis I explore the use of statistical properties of the directed graph describing the set of live data to decide between garbage collection and heap …
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Automating heterogeneous memory management
… these systems may offer new technologies in memory and computation, the general trend of memory performance is falling behind. With the added complexities of heterogeneous systems, achieving good memory performance is now becoming more difficult. Since different memory technologies exhibit …
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Effective memory management for mobile environments
… local</em> heuristics to organize resources like memory, performance, and power. Such a design causes conflicts across all layers of the software stack, calling for the evaluation of VMs and the optimization techniques specific for mobile frameworks.</p> <p>In this dissertation, we study the …
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Compiler Directed Memory Management for Numerical Programs
This thesis presents a new approach to the management of memory hierarchies in the multiprogramming virtual memory system. Memory management related problems are solved partially at compile time, where memory directives are inserted into the object code of a compiled program. The main objectives of …
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Cache memory management in real-time systems
… of performance and predictability. Although memory caching has long been known as a means of increasing system performance, it is typically unpredictable in nature.
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Trackless on-line paging and computer memory management
We consider existing research methodology for dealing with competitiveness analysis of on-line algorithms as well as introduce some newer analysis techniques for testing research hypotheses. Paging is discussed in general and current algorithms are surveyed and analyzed; We also present a new …
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Memory management and rollback recovery in parallel architectures
This thesis examines memory management and rollback recovery in parallel architectures. Three memory management strategies for rapid rollback recovery are studied in this thesis. The first is a cache-based error recovery scheme for shared memory multiprocessors. The second is a design for …
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Region-based memory management for real-time Java
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
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Scalable memory management using a distributed buddy allocator
The recent rise of multicore processors has forced us to reexamine old computer science problems in a new light. As multicores turn into manycores, we need to visit these problems yet again to find solutions that will work on these drastically different architectures. This thesis presents the …
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Organizational memory management for large-scale systems development
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Civil and Environmental Engineering, 1994.
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Activation frame memory management for the Monsoon processor
Thesis: M.S., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1992
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Compiler Memory Management and Compound Function Definition for Multiprocessors
… this type of multiprocessor is the slow global memory. We examine how a compiler can use data dependence information to determine how data is used in a program, and then transform the program to exploit features in the multiprocessor's architecture to reduce the program's memory access time. The …
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Memory Management and Garbage Collection Algorithms for Java-Based Prolog
… like Java which provides its own automatic memory management and safety features such as built--in index checking and array initialization requires a consistent approach to memory management based on a simple ultimate goal: minimizing total memory management time and extra space involved. …
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High Performance Architecture using Speculative Threads and Dynamic Memory Management Hardware
… central processing unit (CPU) performance and memory subsystem performance. More specifically I will describe my research related to the design of an innovative decoupled multithreaded architecture that can be used in multi-core processor implementations. I also address how memory management …
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Gradual Memory Safety
… extends the theory of Gradual Types to include memory safe Region-Types and Region-Based Memory Management. It also makes advancements in the capabilities of Region-Based systems. Lastly, it presents the Svejk language and Hasek Type System.</p>
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Exploring Dynamic Compilation and Cross-Layer Object Management Policies for Managed Language Applications
… additional safety guarantees, automatic memory and thread management, and dynamic program composition, which have largely driven their success. To support and facilitate the use of these features, virtual machines implement a number of services that adaptively manage and optimize …
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Sparsely faceted arrays : a mechanism supporting parallel allocation, communication, and garbage collection
… a new low-level mechanism for naming regions of memory, or facets, on different processors in a distributed, shared memory parallel processing system. Sparsely faceted arrays address the disconnect between the global distributed arrays provided by conventional architectures (e.g. the Cray T3 …
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Intelligent Memory Manager: Towards improving the locality behavior of allocation-intensive applications.
Dynamic memory management required by allocation-intensive (i.e., Object Oriented and linked data structured) applications has led to a large number of research trends. Memory performance due to the cache misses in these applications continues to lag in terms of execution cycles as ever increasing …
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Acceleration of the noise suppression component of the DUCHAMP source-finder
… is the most computationally expensive and memory intensive within DUCHAMP and consequently improvements to it greatly improve overall DUCHAMP performance. We present a high performance, multithreaded implementation of the à trous algorithm with a focus on 'desktop' computing hardware to …
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