Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 51 for “"memory hierarchy"”.
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DeNovo: rethinking the memory hierarchy for disciplined parallelism
… and implementing parallelism. While shared–memory remains a popular programming model due to its global address space, it is plagued with undisciplined programming practices that allow implicit communication and unstructured non-determinism. Such “wild” shared-memory behavior not only makes …
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Exploiting software information for an efficient memory hierarchy
… to address the rising power concerns. Since the memory hierarchy is becoming one of the major consumers of the on-chip power budget in these systems, designing an efficient memory hierarchy is critical to future systems. We identify three sources of inefficiencies in memory hierarchies of today’s …
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A technique for compilation to exposed memory hierarchy
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2000.
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Vector processor virtualization: distributed memory hierarchy and simultaneous multithreading
… the path for performing data shuffle and memory-indexed accesses from the data path for executing other vector instructions that access the memory. This separation speeds up the most common memory access operations by avoiding extra delays and unnecessary stalls. In this multilane-based VP …
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Memory hierarchy and data communication in heterogeneous reconfigurable SoCs
… in contemporary technology development. Memory organization in such heterogeneous reconfigurable architectures becomes very critical. Two primary aspects introduce a sophisticated trade-off. On the one hand, a memory subsystem should provide well organized distributed data structure and …
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Redesigning the memory hierarchy for memory-safe programming languages
We present Hotpads, a new memory hierarchy designed from the ground up for modern, memory-safe languages like Java, Go, and Rust. Memory-safe languages hide the memory layout from the programmer. This prevents memory corruption bugs, improves programmability, and enables automatic memory …
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Common-case optimized memory hierarchy for data centers and HPC systems
The memory hierarchy is predicted to consume up to 40% to 70% of total system power in future data centers and high performance computing (HPC) systems; as such, it is time to rethink memory system designs. Conventional memory system designs in existing systems often seek to provide uniform …
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Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy
… and proposes a cluster-based on-chip memory hierarchy without hardware cache coherence. Programming for such an environment, which can use scratchpads or incoherent caches, is challenging. Hence, this thesis focuses on architecting, programming, and evaluating an on-chip incoherent …
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Design and analysis of a memory hierarchy for a very high performance multiprocessor configuration
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982.
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Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies
… running at a low voltage, leakage in on-chip memory modules contributes substantially to the chip’s power draw. This is unfortunate given that, intuitively, the large multi-level cache hierarchy of a manycore is likely to contain a lot of useless data. An effective way to reduce this problem …
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Exploiting multiprocessor memory hierarchies for operating systems
… the increasing gap between processor speed and memory speed, a sophisticated memory hierarchy is key to high performance. However, the operating system tends to use the memory hierarchy poorly. This thesis presents a comprehensive characterization and optimization of the performance of …
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Refresh reduction in dynamic memories
… (eDRAM). Unfortunately, eDRAM, being a dynamic memory, requires periodic refresh, which ends up consuming substantial energy for large last-level caches. In upcoming architectures that stack a processor die and multiple DRAM dies, DRAM dies experience higher temperatures. Elevated temperatures …
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Efficient Performance Evaluation for Highly Multi-threaded Graphics Processors
… novel software-based approach for monitoring the memory hierarchy performance in highly multithreaded general-purpose graphics processors. The proposed analysis is based on memory traces collected for small snapshots of application execution. A trace-based memory hierarchy model with a Monte Carlo …
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Exploiting on-chip memory concurrency in 3d manycore architectures
… technology trends point to large increases in memory-level concurrency. This in turn affects the design of the multi-core interconnect and organization of the memory hierarchy. The work addresses the need for re-optimization in the presence of this increase in concurrency of the memory system. …
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Cache-oblivious dynamic search trees
… whose leaves point to intervals in a "packed memory structure". We refer to the data structure as a COB-Tree. The COB-Tree supports efficient lookup, as well as efficient amortized insertion and deletion. Efficient implementation of a B-tree requires understanding the cache-line size and page …
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Fabrication and Characterization of HfO2 Based Resistive Random Access Memory Devices
Current technology is dependent on the usage of a memory hierarchy. Primary components include SRAM, DRAM, and Flash. The ordering of these components in the memory hierarchy is dictated by both the cost and the performance of the components. These devices all share two distinct problems in that …
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Simulation of a novel multiprocessor system based on dataflow principles
… has been extended to incorporate a multi-level memory hierarchy and dynamic load balancing. An efficient hardware-based garbage collection mechanism has been proposed. Various design trade-offs are evaluated. The simulation demonstrates that the architecture can support memory access with DRAM …
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Tunable shared-memory abstractions for distributed-memory systems
Distributed memory multiprocessor architectures offer enormous computational power, by exploiting the concurrent execution of many loosely connected processors. Yet, such scalability is not without price. Interface delays and low interconnection bandwidth to the distributed memories make internode …
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Optimization and validation of discontinuous Galerkin Code for the 3D Navier-Stokes equations
… of DG methods are identified, including key memory bottlenecks. A detailed overview of the memory hierarchy on modern CPUs is given along with discussion on optimization suggestions for utilizing the hierarchy efficiently. Other programming suggestions are also given, including the process …
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Loop Transformations for the Optimized Generation of Reconfigurable Hardware
… data-intensive applications on heterogeneous-memory systems; they rather focus on parallelism. This thesis addresses the memory hierarchy problem to high-level transformations of loop structures. The composition of long transformation sequences by combining shorter subsequences is studied …
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