Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 31 for “"memory architecture"”.
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Energy-aware DNN Quantization for Processing-In-Memory Architecture
… energy efficiency of DNN by considering hardware architectures and algorithms together. In this work, a genetic algorithm-based energy-aware DNN quantization framework for Processing-In-Memory (PIM) architectures, named EGQ, is presented. The key contribution of the research is to design a fitness …
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Memory [Architecture] Film: Four Cinematic Events in the City
… unique arise. Those are the moments where our memory is deeply engraved by a particular situation that will come back in our dreams and imaginative processes as an agent image. Four urban events — a space for film edition and writing, an urban stage, a footage archive and park, and a projection …
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Directoryless shared memory architecture using thread migration and remote access
… distributed caches. In order to support shared memory, current many-core CMPs maintain cache coherence using distributed directory protocols, which are extremely difficult and error-prone to implement and verify. Private caches with directory-based coherence also provide suboptimal performance …
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Splash-2 shared-memory architecture for supporting high level language compilers
… to create CCM programs. Many aspects of CCM architectures, such as local memory systems, are not conducive to HLL compiler usage. This thesis proposes and evaluates the use of a shared-memory architecture on a Splash-2 CCM to promote the development and usage of HLL compilers for CCM systems.
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Color reclamation for heap memory coloring scheme in PIPE tagged-memory architecture
Memory safety violations remain a significant hurdle as people try to secure computer software. The PIPE project proposed an approach to securing software by tagging memory and registers with color tags and defining policies in terms of the tags to disallow instructions violating memory safety. …
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Multi-Domain Coincidence Processing and Memory Architecture for Real-Time Geiger Mode LiDAR
… This paper proposes a multi-processor system architecture and memory management techniques for performing orientation-compensated histogram generation and peak detection to filter the LiDAR data stream, removing redundancy and spurious outputs. The multi-processor design, employing custom …
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Algorithm–Hardware Co-Design Of Digital Compute-In-Memory Architecture Supporting Flexible And Temporal N:M Sparsity
… in size and capability, increasing demands on memory, energy, and computation. This has motivated algorithm–hardware co-design approaches for efficient inference, with structured N:M sparsity emerging as a promising method to reduce overhead. However, fixed sparsity configurations across layers …
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Rapid Prototyping of an FPGA-Based Video Processing System
… system as well as to utilize the fastest memory on an FPGA, a sliding window memory architecture is proposed. This memory architecture can be applied to a series of video processing algorithms while the latency between an input pixel and an output pixel is minimized. By comparing my …
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Visual memory
Visual memory supports computer vision applications by efficiently storing and retrieving spatiotemporal information. It is a unique combination of databases, spatial representation and indexing, and temporal representation and indexing. This thesis designs a visual memory architecture that meets …
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Network-on-chip design for a chiplet-based waferscale processor
… details the design of an NoC to enable a shared memory architecture in a chiplet-based wafer scale processor with architectural support for up to 14,336 cores.
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Architectures for photon-mediated quantum information processing
In this thesis, I present architectures for quantum information processing where photons are used as the quantum bit (qubit) or for mediating entanglement between other qubits. The emphasis of this research is to simplify the basic building blocks required in such processors. The all-photonic …
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Speculative Shared -Memory Architectures
… parallel codes. We propose a speculative shared-memory system to extract parallelism from codes for which today's parallelizing compilers fail. We distance ourselves from the existing literature by targeting scalability and modularity: Our hierarchical approach largely abstracts away the …
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Design and evaluation of the Hamal parallel computer
Parallel shared-memory machines with hundreds or thousands of processor-memory nodes have been built; in the future we will see machines with millions or even billions of nodes. Associated with such large systems is a new set of design challenges. Many problems must be addressed by an architecture …
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Unnamed modernisms : national ideologies and historical imaginaries in Beirut's urban architecture
… in a series of historiographic approaches to memory, architecture, and urbanism. This dissertation argues that a critical approach to the city in this context has to come to terms with the omissions that constitute its history and the ambiguities of its multiple political locations. It …
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The memory laboratory : reclaiming and remebering the archeological fragments of Cape Town's original shoreline
… and particularly the role of collective urban memory in reading and understanding public space in the city, as well as being a means of imbuing public space with meaning. This is closely linked to ideas of shared experience, identity and legacy. These ideas are widely discussed and debated in …
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Magnetic logic circuits with high bit resolution for hardware acceleration
… in domain wall logic devices is studied to guide memory and logic applications. Theory, numerical modeling, and experiments on in-plane and perpendicularly magnetized materials demonstrate that the bit resolution, or analog information capacity, of a magnetic nanowire with a single domain wall is …
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Cross-layer methods for energy-efficient inference using in-memory architectures
… challenge. In conventional von Neumann architectures, the energy and latency cost of realizing ML algorithms is dominated by memory accesses. To address this issue, the deep in-memory architecture (DIMA) was proposed, which embeds mixed-signal computation as an integral part of the …
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Common-case optimized memory hierarchy for data centers and HPC systems
The memory hierarchy is predicted to consume up to 40% to 70% of total system power in future data centers and high performance computing (HPC) systems; as such, it is time to rethink memory system designs. Conventional memory system designs in existing systems often seek to provide uniform …
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Performance of Algebraic Multigrid for Parallelized Finite Element DNS/LES Solvers
… GMRES; and on two supercomputers of different memory architecture(distributed and shared memory). This study revealed Fourier space partitioning outperforms physical space partitioning in all problems analyzed, and scales more efficiently as well. These differences were more dramatic on the …
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