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Showing 1 to 1 of 1 for “"low-power FPU"”.

  1. Cross-layer instruction-aware timing error mitigation & evaluation for energy-efficient dependable architectures

    … of pipelined architectures is exploited and a low power security primitive for hardware-rooted device authentication is proposed. To achieve this, DTA-PUF, a novel lightweight physical unclonable function, is introduced.

    qu-belfast Repository record for Cross-layer instruction-aware timing error mitigation & evaluation for energy-efficient dependable architectures (opens in a new tab)