Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 9 of 9 for “"loop delay"”.
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The effects of excess loop delay in continuous-time sigma-delta modulators
… Delta modulators, the problem due to excess loop delay that arises from timing mismatch and parasitic delay still remains unsolved. Thus, the thesis investigates the effects of the excess loop delay. In specific, the sensitivity of various CT-Sigma Delta topologies to the excess loop delay is …
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Phase-locked loop, delay-locked loop, and linear decorrelating detector for asynchronous multirate DS-CDMA system
… and code tracking of a digital phase-locked loop (PLL) and delay-locked loop (DLL), respectively, is investigated in wideband asynchronous multirate DS-CDMA system. Dynamic Partial Correlation (DPC) method is proposed to evaluate the autocorrelation and its power spectrum density (PSD) of the …
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Continuous-Time Delta-Sigma Modulators for Wireless Communication
… for improved robustness against variations in loop delay. An RZ pulse, centered in the clock period, is used in the innermost feedback path which has the highest sensitivity to loop delay, while NRZ pulses are adopted in the outer feedback paths to reduce the sensitivity to clock jitter and …
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A contribution to continuous-time quadrature bandpass sigma-delta modulators for low-IF receivers
… for the design of CT-QBP SDM. Starting from CT loop filter optimization, the equivalent noise shaping transfer function is finally calculated and its stability margin is estimated. Because of the optimization in the CT-domain, this method gives to designer lots of flexibilities for circuit …
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Nonlinear Deadbeat Current Control of a Switched Reluctance Motor
… that accounts for processor latency and PWM delay. The practical problems of loop delay, feedback noise, feedback filtering, and deadbeat controller parameter sensitivity are investigated by linear analysis, simulation, experimental implementation and nonlinear model analysis. Simulation and …
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A subsampling delta-sigma modulator for global navigation satellite systems
… of the effective Quality (Q-factor) of the loop filter prevent conventional CT-ΔΣ modulators to be utilized in subsampling receivers. This thesis proposes a novel CT-ΔΣ modulator at both the system and the circuit level that is capable of compensating for the effects of subsampling. These …
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Low-power high-performance SAR ADC design with digital calibration techniques
… digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.
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Modeling and Design of a Monolithic High Frequency Synchronous Buck with Fast Transient Response
… ASIC. Achieving this requires an accurate loop gain design, especially for monolithically integrated high frequency switching converter since compensator is fixed on silicon and loop delay is comparable with switching cycle. Since DC-DC switching converters are time-varying system, …
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Circuits for time-domain signal processing
… uses a high resolution digitally controlled delay line (DCDL). Background calibration is used to correct interstage gain errors and sequential switching is used to reduce DCDL non-linearity. Fabricated in 65nm CMOS process, the prototype DTC achieves 1.65ps peak integral non-linearity (INL) …