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Showing 1 to 20 of 41 for “"logic design"”.
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Optimizing Programmable Logic Design Security Strategies
A wide variety of design security strategies have been developed for programmable logic devices, but less work has been done to determine which are optimal for any given design and any given security goal. To address this, we consider not only metrics related to the performance of the design …
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Algorithms for Logic Design Automation (Rtcad, Synthesis)
As the complexity of logic circuits which may be placed on an integrated circuit grows, the complexity and length of the design process increases also. Consequently, there have been increased efforts in recent years directed at developing tools to ease design tasks, mostly the physical tasks such …
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Logic Design Methods for Irredundant Mos Networks
Made available in DSpace on 2014-12-13T18:02:06Z (GMT). No. of bitstreams: 1 7913492.pdf: 9772259 bytes, checksum: d1aaeacb841e787cd2fa8b56499068e8 (MD5) Previous issue date: 1978
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Diagnosis and correction of logic design errors
A CAD tool ACCORD has been developed for design verification and design error correction. ACCORD verifies a gate-level implementation of a design in terms of its functional description. If the functionality of an implementation is incorrect, the tool identifies the error locations and makes …
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Multiple-Valued Logic Design in Current-Mode CMOS
Over the last two decades, design using Multiple-Valued Logic (MVL) has been receiving considerable attention. With recent advancements in processing technologies it is now possible to implement higher-radix functions. MVL circuits have shown the potential of improving the use of chip area through …
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A Logic Design Procedure to Facilitate Fault Detection
Made available in DSpace on 2014-12-10T19:06:48Z (GMT). No. of bitstreams: 1 7207058.pdf: 2686298 bytes, checksum: 40a98e38f4a6a2f6279a8b57ee0f82fc (MD5) Previous issue date: 1971
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Sequential logic design using counters as memory elements
… counters are considered as memory elements. Design limitations and design procedures for each type of counter are determined, with emphasis placed on UP/DN/PRESET type counters. It is shown that a presettable counter is capable of realizing any sequential machine. Special considerations …
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Novel RTD-Based Threshold Logic Design and Verification
… have been developed to enhance future circuit design to overcome physical barriers hindering complementary metal-oxide semiconductor (CMOS) technology. Among the emerging nanodevices, resonant tunneling diodes (RTDs) have demonstrated promising electronic features due to their high speed …
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Tunneling Field-Effect Transistors for Low Power Logic: Design, Simulation and Technology Demonstration
… double-gate (DG) TFET with extended source, was designed for drive current enhancement. In addition, Si:C was implemented into Si TFET as the source to ease BTBT and therefore improve the device performance. New substrate material germanium-tin (GeSn), which has small bandgap, was explored for …
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Extension of set-based inference mechanism for predicate logic design constraints with an application to automotive power window design
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2000.
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Discrete Event Control in Manufacturing Automation
In this research, several SCT and design software tools are being developed to provide different services for manufacturing automations. They are FBSCT, supporting software package for supervisory control logic design and verification; Open HMI Builder, an easy-use GUI development tool; and …
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Logic synthesis and optimization algorithms
… size and chip complexity keep increasing, logic design is becoming more complex and it must be automated. The increasing demand for ASIC (Application Specific Integrated Circuits) also needs design efficiency and cost effectiveness which can only be achieved by effective automatic logic …
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A Study of Current Logic Design Problems: Part I, Design of Diagnosable Mos Networks; Part Ii, Minimum Nor (Nand) Networks for Parity Functions of an Arbitrary Number of Variables; Part Iii, Minimum Parallel Binary Adders With Nor (Nand) Gates and Their Extensions to Networks Consisting of Carry-Save Adders
Made available in DSpace on 2014-12-13T18:01:47Z (GMT). No. of bitstreams: 1 7616153.pdf: 11488530 bytes, checksum: 3e5b25aecde14aa552f4cbbf1cb3e4e5 (MD5) Previous issue date: 1976
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Design and automated testing of PCI express interface of proton computed tomography detectors.
… I will propose a transmit-received-engine based logic design proposed by this thesis works at the PCI Express Transaction Layer in collaboration with Xilinx 7 Series FPGAs Integrated Block for PCI Express. By automated testing and results evaluation, the new design can speed up the original …
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Logic optimization of MOS networks
The logic networks that can be put on a single chip continues to grow in size and complexity. There is thus an increasing need for designers to rely on the assistance of computer-aided design tools to provide a fast design turnaround and reduce design errors. Logic design (or logic synthesis) is …
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Design methods for self-repairing digital logic
A systematic approach for the design of self-testable, self-correcting, self-repairing and self-healing digital systems was proposed. This self-test/self-repair methodology is accomplished autonomously, in a distributed fashion, so that it can scale as the size of the system grows. Modular …
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Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures
… less noise and EMI emission, and easy design reuse are some of the benefits of these circuits. NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms that has been shown to be a promising method for designing delay-insensitive asynchronous circuits. …
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Performance-driven placement and routing algorithms
… dissipation becomes an important issue in VLSI design, it is desirable for the signals to arrive at the inputs of the modules at the same time in order to reduce the number of unwanted transient switches. To minimize the signal arrival times of the primary output pins and the signal skews at the …
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Design synthesis for dynamically reconfigurable logic systems
Dynamic reconfiguration of logic circuits has been a research problem for over four decades. While applications using logic reconfiguration in practical scenarios have been demonstrated, the design of these systems has proved to be a difficult process demanding the skills of an experienced …
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