Global ETD Search
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Showing 1 to 12 of 12 for “"linear equalizer"”.
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Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology
… 3.1 link in 65 nm CMOS technology. Two types of equalizers are implemented: a continuous time linear equalizer (CTLE) and a 1-tap full-rate decision feedback equalizer (DFE). The combined CTLE and DFE architecture is simulated with an rms receiver clock jitter of 5.3 ps and achieves a BER < …
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Intercarrier Interference Suppression for the OFDM Systems in Time-Varying Multipath Fading Channels
… motivates us to design the low-complexity Q-tap equalizers, namely, Minimum Mean Square Error (MMSE) linear equalizer and Decision Feedback (DF) non-linear equalizer to mitigate the ICI. Simulation results show that both Q-tap equalizers can improve the system performance in the sense of symbol …
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Robust acoustic signal detection and synchronization in a time varying ocean environment
… The current common methods include using a linear frequency modulated chirped pulse or maximal length sequence as a detection pulse, then match filtering to that signal. In higher signal to noise ratio (SNR) environments (~0 dB and higher) this has been a suitable solution. As the SNR drops …
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Robust acoustic signal detection and synchronization in a time varying ocean environment
… The current common methods include using a linear frequency modulated chirped pulse or maximal length sequence as a detection pulse, then match filtering to that signal. In higher signal to noise ratio (SNR) environments (- 0 dB and higher) this has been a suitable solution. As the SNR drops …
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An information theoretic study of reduced-complexity receivers for intersymbol interference channels
… Signal-to-Noise Ratio necessitating the use of a linear equalizer at the front end of the decoder. We derive the achievable rates for these schemes and optimize under complexity constraints the design of the equalizer and the receiver. Overall, two ensemble of codes are considered: the Independent …
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Sparse equalizer filter design for multi-path channels
… thesis, sparse Finite Impulse Response (FIR) equalizers are designed for sparse multi-path channels under a pre-defined Mean Squared Error (MSE) constraint. We start by examining the intrinsic sparsity of the Zero Forcing equalizers and the FIR Minimum MSE (MMSE) equalizers. Next the …
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Turbo equalization using message passing methods with higher order modulation signaling
… equalization algorithm which consists of MAP equalizer and MAP decoder. However, this algorithm gives rise to an impractical computational complexity. The computational burden leads us to consider the turbo equalization based on minimum mean squared error (MMSE) linear equalizer which reduces …
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Low-power and energy-efficient wireline receivers
… and temperature variations. A continuous-time linear equalizer (CTLE) is used to compensate for intersymbol interference (ISI). The CDR prototype fabricated in 65 nm CMOS recovers 15.2 Gb/s data using only differential 3.8 GHz clock and achieves total power consumption of 29 mW, which …
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Equalization in continuous and discrete time for high speed links using 65 nm technology
… (CMOS), especially on designing both Tx and Rx equalizers. The equalizer is a key component in insuring communication as signals that propagate through some channel will have to endure insertion loss and cross talk, where this can cause two major problems: larger rise/fall times and lower signal …
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A class of batch-iterative methods for the equalization of intersymbol interference channels
A class of nonlinear receivers is proposed to equalize intersymbol interference (ISi) channels in a batch-iterative fashion. The iterated-decision or multipass equalizer uses symbol decisions made during the previous iteration to cancel out both precursor and postcursor ISi during the current …
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Digital communication and control circuits for 60ghz fully integrated CMOS digital radio
… parametric tuning for digital modules such as linear equalizer, Gain Control loops (AGC, VGA), etc. Ultra high speed digital Input-Output buffers are used to provide an external data interface to the radio chipset. These high speed I/Os are also used in the gbps (gigabit-per-second) link for …
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Low-power high-performance SAR ADC design with digital calibration techniques
… under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which …