Global ETD Search
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Showing 1 to 6 of 6 for “"latency tolerance"”.
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Compilation-based prefetching for memory latency tolerance
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1992.
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Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands
This dissertation presents a novel decoupled latency tolerance technique for 1000-core data parallel processors. The approach focuses on developing instruction latency tolerance to improve performance for a single thread. The main idea behind the approach is to leverage the compiler to split the …
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Impostors for Parallel Interactive Computer Graphics
… the impostors technique. Impostors increase the latency tolerance of an interactive rendering system, which allows us to use the power of a parallel machine even at high resolutions and framerates. Impostors also decrease the required rendering bandwidth, which makes possible the interactive use …
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Visible synchronization based cache coherence
… may be lost while waiting for a high latency synchronization or memory operation to complete, or a stall in an instruction pipeline to be dealt with. Latency is avoided by bringing data to a nearby locale for future reference (e.g., caching) while latency is tolerated by overlapping …
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Prefetching for complex memory access patterns
… those in big data, are heavily memory-latency bound. This is because of both irregular memory accesses, which have no discernable pattern in their memory addresses, and large data sets that cannot fit in any cache. However, this need not be a barrier to high performance. With some data …
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Efficient memory-level parallelism extraction with decoupled strands
We present Outrider, an architecture for throughput-oriented processors that exploits intra-thread memory-level parallelism (MLP) to improve performance efficiency on highly threaded workloads. Outrider enables a single thread of execution to be presented to the architecture as multiple decoupled …