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Showing 1 to 4 of 4 for “"hybrid hardware/software"”.

  1. Evaluating the Feasibility of Transaction Scheduling via Hardware Accelerators

    … of accelerating transaction scheduling via hardware, leveraging FPGAs to ofoad scheduling logic from the CPU. We revisit Puppetmaster, a hardware transaction scheduler, and present a redesigned architecture emphasizing deployability, modularity, and evaluation. We implement both an optimized …

    mit Repository record for Evaluating the Feasibility of Transaction Scheduling via Hardware Accelerators (opens in a new tab)

  2. Record and deterministic replay of parallel programs on multiprocessors

    … key requirement for many use cases of RnR. While software can often be used to record program inputs with low overhead, it can incur significant overhead to record memory-access interleaving. To reduce this overhead, hardware-assisted RnR techniques have been proposed. The main challenge here is …

    uiuc Repository record for Record and deterministic replay of parallel programs on multiprocessors (opens in a new tab)

  3. Diseño e implementación en hardware reconfigurable de un sistema de reconocimiento de gestos de la mano basado en visión por computador

    … por computador y el diseño de su implementación hardware. El propósito del reconocimiento de gestos es proporcionar a una computadora la capacidad de detectar gestos realizados por una persona. Esta tarea, innata para el ser humano, ha resultado ser compleja y difícil de automatizar. Entre las …

    upc-spain Repository record for Diseño e implementación en hardware reconfigurable de un sistema de reconocimiento de gestos de la mano basado en visión por computador (opens in a new tab)

  4. Low-cost error detection through high-level synthesis

    … in the integration of a wide variety of complex hardware accelerators in SoCs. Thus the challenge is to design complex, custom hardware that is efficient, but also correct and reliable. High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from …

    uiuc Repository record for Low-cost error detection through high-level synthesis (opens in a new tab)