Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 72 for “"high-level synthesis"”.
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Task scheduling in high-level synthesis
High-level synthesis becomes increasingly important in the area of VLSI CAD. This thesis addresses scheduling and allocation in high-level synthesis. Specifically, we study the problem of register allocation in the presence of conditional blocks, such as if and case blocks and loops in the data …
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Trustworthy system development through high-level synthesis
Major processor manufacturers have embraced the high-level synthesis (HLS) design philosophy. HLS offers the potential to explore the design space of electronic circuits and systems more efficiently than traditional methods. In this thesis, we investigate the ap-plication of HLS to …
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VAST-LP: clock gating in high-level synthesis
High-level synthesis (HLS) promises high-quality hardware with minimal develop- ment e ort. In this thesis, we evaluate the current state-of-the-art HLS engine VAST and propose a method to generate clock-gating-friendly RTL code for downstream logic synthesis tools. We use one-hot-key encoding …
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Low-cost error detection through high-level synthesis
… is efficient, but also correct and reliable. High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from the high-productivity software domain to the hardware design process. Much research has been done on high-level synthesis efficiency …
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Scheduling and allocation problems in high-level synthesis
Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studied in this thesis. Specifically, we study (1) the problem of scheduling dataflow graphs with conditional branches; (2) the problem of utilizing multi-port memories in data path synthesis; (3) the …
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Scalable High-Level Synthesis for AI accelerator design
Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-05-01
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Temperature and Interconnect Aware Unified Physical and High Level Synthesis
… is the development of unified physical and high-level synthesis techniques for the design of ASICs with optimal chip temperatures and interconnect delays. Thermal issues are becoming a serious problem in high-performance VLSI circuits, adversely impacting performance, reliability, power …
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Improved Algorithms for High-Level Synthesis and Their Parallel Implementations
In the third part of the thesis, two parallel algorithms for simultaneous scheduling, binding and floorplanning algorithm are presented. Experimental results are reported on an IBM SP-2 multicomputer, with close to linear speedups for a set of benchmark circuits, while giving solutions of almost …
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Robust and reliable hardware accelerator design through high-level synthesis
… is efficient, but also correct and reliable. High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from the high-productivity software domain to the hardware design process. Much research has been done on high-level synthesis efficiency …
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FPGA acceleration of short read alignment with high-level synthesis
… 2, an aligner that is already very popular and high-performing. Through the use of OpenCL, it is possible to parallelize this application for both GPU and FPGA by using the same code. Several different levels of parallelism are implemented in order to achieve speedup on Bowtie 2.
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From Software Threads to Parallel Hardware with LegUp High-level Synthesis
High-level synthesis (HLS) can automatically synthesize software to hardware. With the design specification in software, HLS can reduce the lengthy design cycles of hardware, and make the performance and energy-efficiency benefits of hardware accessible to those without hardware skills. Since the …
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Accelerating path planning algorithms with high level synthesis tools and FPGAs.
… how to design a path planning algorithm in a high level language, then convert the algorithm into hardware description languages using high level synthesis tools. This design framework will be used to demonstrate the acceleration of a genetic algorithm.
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Open-source high-level synthesis of tensorflow dataflow graphs using LegUp
… into FPGA accelerators using the open-source high-level synthesis (HLS) tool LegUp. The Tensorflow computation graph is represented translated from an intermediate representation in Tensorflow's Accelerated Linear Algebra (XLA) compiler called High Level Optimizer (HLO). This is translated …
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High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs
… which are tedious and time consuming. High Level Synthesis (HLS) enables designers to synthesize optimized FPGA hardware from algorithm specifications in programming languages such as C/C++. This substantially reduces the design cost and time. In this thesis, the Altera SDK for OpenCL …
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Making acceleration more amenable with novel high-level synthesis techniques for FPGAs
L'abstract è presente nell'allegato / the abstract is in the attachment
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Hierarchical and scalable bus architecture generation on FPGAs with high-level synthesis
… reports. Design space exploration among multilevel granularity parallelisms is performed to get the system's best performance, with which a comparison with GPU is made. Our system can achieve at most 2.08 performance improvement when compared with the execution latency on GPU.
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Chimera: An efficient design space exploration tool for FPGA high-level synthesis
… and power efficiency. However, with the high flexibility comes the difficulty in design and optimizations. Conventionally, the FPGA designs are written in low-level hardware descriptive languages, which means creating larger designs with complex behavior is extremely difficult. Therefore, …
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Combined Word-Length Allocation and High-Level Synthesis of Digital Signal Processing Circuits
This work is focused on the synthesis of Digital Signal Processing (DSP) circuits usingc specific hardware architectures. Due to its complexity, the design process has been subdivided into separate tasks, thus hindering the global optimization of the resulting systems. The author proposes the study …
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High-level synthesis and its application in the design of Reed-Solomon decoders
… about by recent advanced in VLSI technology. High-level Synthesis (HLS) is a major part of VLSI design process. Its techniques can be used to yield an optimal result in the design. Yet, major applications of HLS methods are on digital filters or DSP circuits. Arithmetic in these circuits are …
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