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Showing 1 to 20 of 3853 for “"high-level"”.

  1. High level data fusion

    … Better performance is possible using probability level fusion as long as the probabilities are accurate. Of particular interest is the prevalence of overconfidence and the effect it has on fused performance. The production of accurate probabilities from poor quality data forms the latter part of …

    aston Repository record for High level data fusion (opens in a new tab)

  2. High-Level Power Estimation

    High-level power estimation requires high-level predictions of circuit average activity, area, and delay, in order to estimate power. The main contribution of this research is development of predictors (estimators) for activity, area, and delay for combinational circuits, thus making it possible to …

    uiuc Repository record for High-Level Power Estimation (opens in a new tab)

  3. A high level disc controller

    … This essentially combines the conventional low-level backing store interface with a special purpose processor which handles all file routines. This dissertation demonstrates how such a structure can be implemented using current technology, and will evaluate its inherent advantages.

    cape-town Repository record for A high level disc controller (opens in a new tab)

  4. International migration of high level manpower

    Digitized by Kansas Correctional Industries

    ksu-retro Repository record for International migration of high level manpower (opens in a new tab)

  5. On High Level Digital System Design

    Made available in DSpace on 2014-12-10T19:07:25Z (GMT). No. of bitstreams: 1 7511696.pdf: 3349236 bytes, checksum: 07b1a6bf1f075f4458d64886f414ee97 (MD5) Previous issue date: 1974

    uiuc Repository record for On High Level Digital System Design (opens in a new tab)

  6. Task scheduling in high-level synthesis

    High-level synthesis becomes increasingly important in the area of VLSI CAD. This thesis addresses scheduling and allocation in high-level synthesis. Specifically, we study the problem of register allocation in the presence of conditional blocks, such as if and case blocks and loops in the data …

    uiuc Repository record for Task scheduling in high-level synthesis (opens in a new tab)

  7. Water borne transport of high level nuclear waste in very deep borehole disposal of high level nuclear waste

    … if it is a reasonable method of storing high level nuclear waste for an extended period of time. The objective of this thesis is to determine the escape mechanisms of radionuclides and to determine if naturally occurring salinity gradients could counteract this phenomenon. Because of the …

    mit Repository record for Water borne transport of high level nuclear waste in very deep borehole disposal of high level nuclear waste (opens in a new tab)

  8. Leakage Models for High Level Power Estimation

    In heutigen sub-100nm CMOS Systemen sind Leckströme von hoher Bedeutung. Diese können auf Transistorebene langsam aber genau (BSIM oder PSP) und auf der Gatter-Ebene schneller aber unter Vernachlässigung wichtiger Parameter (Liberty) vorhergesagt werden. In dieser Arbeit werden Modelle auf RT Ebene …

    oldenburg Repository record for Leakage Models for High Level Power Estimation (opens in a new tab)

  9. Trustworthy system development through high-level synthesis

    Major processor manufacturers have embraced the high-level synthesis (HLS) design philosophy. HLS offers the potential to explore the design space of electronic circuits and systems more efficiently than traditional methods. In this thesis, we investigate the ap-plication of HLS to …

    nps Repository record for Trustworthy system development through high-level synthesis (opens in a new tab)

  10. High level indole signalling in Escherichia coli

    … cases, E. coli responds to a low, persistent level of indole (0.5-1 mM), similar to the concentration found in an E. coli culture supernatant in stationary phase (typically 0.3-0.8 mM). Recently, it has been shown that much higher concentrations of indole (3-5 mM) inhibit cell division by …

    cambridge Repository record for High level indole signalling in Escherichia coli (opens in a new tab)

  11. High level compilation for gate reconfigurable architectures

    … it is past time to raise this abstraction level. The physical hardware in gate-reconfigurable architectures is all low level - individual wires, bit-level functions, and single bit registers - hence one should look to the fetch-decode-execute machinery of traditional computers for higher …

    mit Repository record for High level compilation for gate reconfigurable architectures (opens in a new tab)

  12. Verified Scheduling Via High-Level Scheduling Rewrites

    … a set of core constructs for expressing high-level computation detail and a set of what we call reshape operators, which can be derived from core constructs but trigger low-level decisions about storage patterns and ordering. We will demonstrate that not only is this system capable of …

    mit Repository record for Verified Scheduling Via High-Level Scheduling Rewrites (opens in a new tab)

  13. High-Level CSP Model Compiler for FPGAs

    … design time has subsequently raised a need for high-level synthesis design methodologies that raise the design to a higher level of abstraction. Higher level of abstraction helps in increasing the predictability and productivity of the design and reduce the number of bugs due to human-error. It …

    vt Repository record for High-Level CSP Model Compiler for FPGAs (opens in a new tab)

  14. A high level approach to Arabic sentence recognition

    … system is a fully integrated system; a word level recogniser (baseline system) integrated with linguistic knowledge post-processing module. The presented baseline system is holistic word-based recognition approach characterised as probabilistic ranked task. The output of the system is …

    nott-trent Repository record for A high level approach to Arabic sentence recognition (opens in a new tab)

  15. Automatic Time-Bound Analysis for High-Level Languages

    … important, and being able to do so for high-level languages is particularly desirable. This dissertation presents a general approach for automatic and accurate time-bound analysis for high-level languages, combining methods and techniques studied in theory, languages, and systems. The …

    iu Repository record for Automatic Time-Bound Analysis for High-Level Languages (opens in a new tab)

  16. Stress and coping among high-level adolescent golfers

    The overall purpose of this research programme was to examine how international adolescent golfers cope with performance related stressors. As such, three interrelated studies were designed to pursue this purpose.The purpose of Study 1 was to examine instances when international adolescent golfers' …

    hull Repository record for Stress and coping among high-level adolescent golfers (opens in a new tab)

  17. High level behavioural modelling of boundary scan architecture.

    … developed and implemented in 'C'; ii) A high level model of the Boundary Scan Test Architecture implemented in 'VHDL'. The parsing and insertion algorithm is developed to deal with identifying the design Input/Output (I/O) terminals, their types and the order they appear in the ASIC …

    bournemouth Repository record for High level behavioural modelling of boundary scan architecture. (opens in a new tab)

  18. VAST-LP: clock gating in high-level synthesis

    High-level synthesis (HLS) promises high-quality hardware with minimal develop- ment e ort. In this thesis, we evaluate the current state-of-the-art HLS engine VAST and propose a method to generate clock-gating-friendly RTL code for downstream logic synthesis tools. We use one-hot-key encoding …

    uiuc Repository record for VAST-LP: clock gating in high-level synthesis (opens in a new tab)

  19. Low-cost error detection through high-level synthesis

    … is efficient, but also correct and reliable. High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from the high-productivity software domain to the hardware design process. Much research has been done on high-level synthesis efficiency …

    uiuc Repository record for Low-cost error detection through high-level synthesis (opens in a new tab)

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