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Showing 1 to 11 of 11 for “"hardware software codesign"”.

  1. A methodology for hardware-software codesign

    Special purpose hardware is vital to embedded systems as it can simultaneously improve performance while reducing power consumption. The integration of special purpose hardware into applications running in software is difficult for a number of reasons. Some of the difficulty is due to the …

    mit Repository record for A methodology for hardware-software codesign (opens in a new tab)

  2. A unified model for hardware/software codesign

    … always built with parts implemented in both hardware and software. Market forces encourage such systems to be developed with dierent hardware-software decompositions to meet dierent points on the price-performance-power curve. Current design methodologies make the exploration of dierent …

    mit Repository record for A unified model for hardware/software codesign (opens in a new tab)

  3. Optimizations for acyclic dataflow graphs for hardware-software codesign

    Most computationally-intensive programs spend a majority of their time within a small portion of the executable code. A novel computer architecture and compiler, called PRISM-2, is introduced, which improves the performance of these programs by synthesizing the "most often" executed instructions. …

    vt Repository record for Optimizations for acyclic dataflow graphs for hardware-software codesign (opens in a new tab)

  4. FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation

    An FPGA-based experiment platform for hardware-software codesign experiments was developed. The proposed platform would be used by an engineer who can be affiliated with academia, research or industry for codesign experiments or hardware emulation. The platform utilizes a combination of a …

    byu Repository record for FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation (opens in a new tab)

  5. Template-based hardware-software codesign for high-performance embedded numerical accelerators

    … layers. We build flexible structures at the hardware, software and algorithm level, and approach the solution through design space exploration. To do this efficiently we use a template-based hardware-software development flow. The main incentive for template use is, as in software

    mit Repository record for Template-based hardware-software codesign for high-performance embedded numerical accelerators (opens in a new tab)

  6. Resource-constrained and Resource-efficient Modern Cryptosystem Design

    … I propose an area-efficient partitioning and a Hardware/Software codesign for its implementation. The results of these implemented modern cryptosystems validate the advantage of my approach by quantifying the drastic improvements over the previous best.

    vt Repository record for Resource-constrained and Resource-efficient Modern Cryptosystem Design (opens in a new tab)

  7. Secure and Efficient Implementations of Cryptographic Primitives

    … algorithms are implemented in either software or hardware, they are known to be vulnerable to various implementation attacks. Although many countermeasures have been proposed, selecting and integrating a set of countermeasures thwarting multiple attacks into a single design is far from …

    vt Repository record for Secure and Efficient Implementations of Cryptographic Primitives (opens in a new tab)

  8. Highly Efficient Neuromorphic Computing Systems With Emerging Nonvolatile Memories

    <p>Emerging nonvolatile memory based hardware neuromorphic computing systems have enabled the implementation of general vector-matrix multiplication in a manner to fuse computation and memory at the same physical location. However, there remain three major challenges in designing such neuromorphic …

    duke Repository record for Highly Efficient Neuromorphic Computing Systems With Emerging Nonvolatile Memories (opens in a new tab)

  9. Entwurf, Methoden und Werkzeuge für komplexe Bildverarbeitungssysteme auf Rekonfigurierbaren System-on-Chip-Architekturen

    … Systeme aus einer gezielten Synergie aus Software- und Hardwarekomponenten aufgebaut werden. Die Konstruktion solcher System ist jedoch komplex und viele Lösungen, wie zum Beispiel grobgranulare Architekturen oder anwendungsspezifische Programmiersprachen, sind oft zu akademisch für einen …

    potsdam-diss Repository record for Entwurf, Methoden und Werkzeuge für komplexe Bildverarbeitungssysteme auf Rekonfigurierbaren System-on-Chip-Architekturen (opens in a new tab)

  10. A Neural Signal Processor for Low-Latency Spike Inference

    … spike inference. The second is a piece of software (Spiketag) that runs on a PC, communicates with the NSP, and generates a spike-sorted model to guide the real-time spike inference. The NSP provides clocks and control signals to five 32-channel INTAN RHD2132 chips to manage the acquisition …

    cambridge Repository record for A Neural Signal Processor for Low-Latency Spike Inference (opens in a new tab)