Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 60 for “"hardware accelerators"”.
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Exocompilation for Productive Programming of Hardware Accelerators
… kernel libraries are critical to exploiting accelerators and specialized instructions in many applications. Because compilers are difficult to extend to support diverse and rapidly-evolving hardware targets, and automatic optimization is often insufficient to guarantee state-of-the-art …
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Designing Hardware Accelerators for Solving Sparse Linear Systems
… optimizing linear solvers for high performance hardware. However, despite their efforts, existing hardware has let them down. State-of-the-art linear solvers often utilize < 1% of available compute throughput on existing architectures such as CPUs and GPUs. There are many different algorithms …
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Evaluating the Feasibility of Transaction Scheduling via Hardware Accelerators
… of accelerating transaction scheduling via hardware, leveraging FPGAs to ofoad scheduling logic from the CPU. We revisit Puppetmaster, a hardware transaction scheduler, and present a redesigned architecture emphasizing deployability, modularity, and evaluation. We implement both an optimized …
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Energy Efficient Hardware Accelerators for Packet Classification and String Matching
… algorithms and energy efficient high throughput hardware accelerators that implement packet classification and fixed string matching. These computationally heavy and memory intensive tasks are used by networking equipment to inspect all packets at wire speed. The constant growth in Internet usage …
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Memristor-based hardware accelerators: from device modeling to AI applications
L'abstract è presente nell'allegato / the abstract is in the attachment
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Optimized ray tracing for real time use without hardware accelerators
… images. However, in recent years graphics hardware has begun including specialized cores to accelerate ray tracing, an alternative rendering solution to rasterization and a type of light transport simulation. Ray tracing is generally the more desirable choice due to its ability to present …
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Performance and Energy Efficiency Insights in LLM Inference Across Hardware Accelerators
… LLM serving often depends on specialised hardware acceleration. While GPUs continue to dominate, domain-specific accelerators like TPUs and dataflow architectures are becoming increasingly compelling alternatives. In this thesis, we provide a comprehensive empirical performance study of …
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New techniques for the Reliability Evaluation of AI-oriented Hardware Accelerators
L'abstract è presente nell'allegato / the abstract is in the attachment
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Designing Highly-Efficient Hardware Accelerators for Robust and Automatic Deep Learning Technologies
… which poses a daunting challenge to traditional hardware platforms, such as CPUs/GPUs. The second issue lying in the conventional DNN applications is the laboring-intensive design period. The actual architecture design of a DNN model demands significant amount of efforts and cycles from machine …
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Accelerating Quantized DNNs with Dedicated Hardware Accelerators and RISC-V Processors Using Precision-Scalable Multipliers
L'abstract è presente nell'allegato / the abstract is in the attachment
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Efficient Deep Learning Inference: A Digital Hardware Perspective - Evaluating and improving performance and efficiency of artificial and spiking neural networks hardware accelerators
L'abstract è presente nell'allegato / the abstract is in the attachment
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Hardware Accelerator Generation Framework for Cryptographic Primitives
… for secure communication; thus, dedicated hardware accelerators are required in resource and latency-constrained environments. High-Level Synthesis (HLS) generates hardware from high-level implementations in languages like C, enabling the rapid prototyping and evaluation of designs, leading …
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GePSeA: A General-Purpose Software Acceleration Framework for Lightweight Task Offloading
Hardware-acceleration techniques continue to be used to boost the performance of scientific codes. To do so, software developers identify portions of these codes that are amenable for offloading and map them to hardware accelerators. However, offloading such tasks to specialized hardware …
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FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems
… applications. This trend has led to emergence of hardware accelerators in embedded systems. While the processing power of dedicated hardware modules seems appealing, they require significant effort of development and integration to gain performance benefit. Thus, it is prudent to investigate and …
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An Energy and Area Estimation Plugin for Accelerator Architecture Simulation
Development of domain-specific hardware accelerators has been an important focus for high performance computing research in recent years, enabling significant gains in a variety of practical applications. Of particular interest is accelerator design for applications involving sparse data. Such …
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Parallel algorithms for placement and routing in VLSI design
… of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. In this thesis, we propose two new parallel algorithms for two VLSl synthesis tasks, standard cell placement and global routing.
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Heterogeneous multiprocessor pipeline design for H.264 video encoder
… (ASIPs) with local and shared memories, and hardware accelerators (in the form of custom instructions). Our platform can be configured to use a particular number of ASIPs (slices/Group of Macroblocks per video frame) for a specific video resolution at design-time. The MPSoC architecture is …
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A Reconfigurable FPGA Overlay Architecture for Matrix-Matrix Multiplication
… language has inspired many attempts to develop hardware accelerators for matrix-matrix multiplication. Both application-specific integrated circuits (ASICs), and field-programmable arrays (FPGAs) are used for this purpose. However, a trade-off between the two platforms is that ASICs provide …
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Branch Prediction For Network Processors
… computation intensive tasks to dedicated hardware logic or through increased parallelism. While parallelism retains flexibility, challenges such as load-balancing limit its scope. On the other hand, hardware offloading allows complex algorithms to be implemented at high speed but sacrifice …
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