Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 71 for “"hardware acceleration"”.
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Efficient AI hardware acceleration
Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-04-12 without embargo terms
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Hardware acceleration of neural graphics
Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-02-04 without embargo terms
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Inference neural network hardware acceleration techniques
A number of recent researches focus on designing accelerators for popular deep learning algorithms. Most of these algorithms heavily involve matrix multiplication. As a result, building a neural processing unit (NPU) beside the CPU to accelerate matrix multiplication is a popular approach. The NPU …
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Hardware acceleration of Monte Carlo-based simulations
… intensive applications. The use of FPGAs for hardware acceleration is an active research field. However, there are still several challenges concerning the use of FPGAs as accelerators: • Availability of Cores. • Capability and performance of FPGAs. • Methods, algorithms and techniques suited …
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Hardware acceleration of the SAMtools variant caller
This thesis presents a design for a hardware-accelerated implementation of the SAMtools variant caller on an FPGA. It also includes a performance analysis of the algorithm and a proposed change to its software architecture to improve performance. SAMtools is normally invoked as a two-step command, …
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Hardware acceleration for sparse Fourier image reconstruction
… In this paper we present an RC-based hardware accelerator for an important medical imaging algorithm: iterative sparse Fourier image reconstruction. We transform the algorithm to exploit massive parallelism available in the FPGA fabric. Our design allows different ways of chaining …
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SERenaDE: Hardware Acceleration of Cloud Serialization Frameworks
… process. Prior work has proposed specialized hardware accelerators to address these overheads. While these proposals achieve considerable speedups, they are expensive in terms of verification, fabrication, and deployment, and often hardcode too many details about the (de)serialization …
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The Software and Hardware Acceleration for Interior Tomography
… it is necessary to develop software and hardware methods to accelerate the iterative reconstruction algorithms. The main methods to accelerate iterative reconstruction algorithms can be either expedite the convergence rate of the algorithm mathematically or directly accelerating the most …
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Towards unified and transparent general-purpose hardware acceleration
Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-08-01
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Energy-Efficient Real-Time Hardware Acceleration for Gaussian Fitting
… of an FPGA (Field Programmable Gate Array)-based hardware accelerator that enables Gaussian fitting based on the SPGF algorithm with 10.4× lower energy per image (based on post-implementation power analysis), compared to the original, software implementation. By using fixed-point numerical …
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Scalable and Broad Hardware Acceleration through Practical Speculative Parallelism
… the performance improvements it once did. Hardware accelerators, which tailor their architecture to a specific application or domain, have emerged as an attractive approach to improve performance. Unfortunately, current accelerators have been limited to domains such as deep learning, where …
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Hardware acceleration of NetApp virtual tape library deduplication algorithm
… environment can also easily be adapted for the acceleration of other shifting window algorithms. I tested the algorithm in simulation to verify its results as well as to estimate the speed at which the algorithm could process data.
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Hardware Acceleration for Real-Time Compression of 3D Gaussians
… limited on-board battery capacity, the computer hardware used in small robots is much less capable than the high-powered GPUs that the 3DGS algorithm was originally developed on, having both less compute and memory capacity and bandwidth. While there has been work developing specialized compute …
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Novel Approaches to Automatic Hardware Acceleration of High-Level Software
… improving application performance. Yet, hardware development for FPGAs is notoriously difficult and far-removed from software design, leaving this potential unrealised. This thesis explores two major techniques to address this gap. The first technique is the seamless integration of …
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A hardware acceleration technique for gradient descent and conjugate gradient
… we target. In this thesis we present a novel hardware architecture for accelerating gradient descent and other similar algorithms. To support this architecture, we also present a sparse matrix-vector storage format, and software support for utilizing the format, so that it can be e ciently …
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High-efficiency and high-usability heterogeneous hardware acceleration with FPGAs
The student, Sitao Huang, submitted this Dissertation for approval on 2021-07-16 at 16:21.
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Magnetic logic circuits with high bit resolution for hardware acceleration
… domains of a wire, for applications to hardware acceleration. A domain wall logic device takes current on the input, which moves a magnetic domain wall to a position in a ferromagnetic wire, and this position is the nonvolatile data token read as an output current through a magnetic …
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FPGA-based hardware acceleration for a key-value store database
… database performance is the use of dedicated hardware to effectively complement or replace software to 'accelerate' the overall system. This thesis investigates the use of a Field-Programmable Gate Array (FPGA) as a hardware accelerator for a key-value database. Utilized as a platform of …
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Hardware acceleration of the pair HMM algorithm for DNA variant calling
Made available in DSpace on 2017-08-10T19:16:15Z (GMT). No. of bitstreams: 2 HUANG-THESIS-2017.pdf: 3198752 bytes, checksum: 355bc51ce749cb631e269cc6116f3c3f (MD5) LICENSE.txt: 4208 bytes, checksum: 29aa487d1a5b8c7beed523d9c3a35801 (MD5) Previous issue date: 2017-04-26
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