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Showing 1 to 20 of 38 for “"hardware/software co-design"”.

  1. Hardware/Software Co-Design via Specification Refinement

    System-level design is an engineering discipline focused on producing methods, technologies, and tools that enable the specification, design, and implementation of complex, multi-discipline, and multi-domain systems. System-level specifications are as abstract as possible, defining required system …

    ku Repository record for Hardware/Software Co-Design via Specification Refinement (opens in a new tab)

  2. Hardware-Software Co-Design for Sensor Nodes in Wireless Networks

    … tools for analyzing and evaluating different design options for wireless sensor networks (sensornets) and hence, have been intensively studied in the past decades. However, existing simulators only support evaluations of protocols and software aspects of sensornet design. They cannot …

    vt Repository record for Hardware-Software Co-Design for Sensor Nodes in Wireless Networks (opens in a new tab)

  3. Hardware software co-design of machine learning accelerators using univariate functions

    As neural networks grow in complexity, efficient hardware-software co-design is crucial for balancing performance and resource constraints, especially for edge devices and FPGA accelerators. This thesis investigates optimization techniques for hardware-awaretraining and model compression using …

    umn Repository record for Hardware software co-design of machine learning accelerators using univariate functions (opens in a new tab)

  4. Automated communication and floorplan-aware hardware/software co-design for SoC

    The main objective of modern SoC (system-on-chip) designs is to achieve high-performance while maintaining low power consumption and resource usage. However, achieving such a goal is a difficult and time-consuming engineering task due to the vast design space of hardware accelerators and HW/SW task …

    uiuc Repository record for Automated communication and floorplan-aware hardware/software co-design for SoC (opens in a new tab)

  5. Practical Cryptographically Private and Verifiable Computation through Hardware-Software Co-Design

    Fully Homomorphic Encryption (FHE) and Verifiable Computation (VC) enable offloading computation to untrusted servers with cryptographic privacy and integrity guarantees. Despite their attractive security properties, FHE and VC are not widely adopted because (1) they suffer prohibitive performance …

    mit Repository record for Practical Cryptographically Private and Verifiable Computation through Hardware-Software Co-Design (opens in a new tab)

  6. Hardware/Software Co-Design Architecture and Implementations of MIMO Decoders on FPGA

    … great attentions in the area of wireless communications. The hardware implementation of MIMO decoders becomes a challenging task as the complexity of the MIMO system increases. This thesis presents hardware/software co-design architecture and implementations of two typical lattice decoding …

    uno Repository record for Hardware/Software Co-Design Architecture and Implementations of MIMO Decoders on FPGA (opens in a new tab)

  7. Scaling sequential code with hardware-software co-design for fine-grain speculative parallelization

    Multicores are now ubiquitous, but most programmers still write sequential code. Speculative parallelization is an enticing approach to parallelize code while retaining the ease and simplicity of sequential programming, making parallelism pervasive. However, prior speculative parallelizing …

    mit

  8. Dataflow Analysis and Optimization of High Level Language Code for Hardware-Software Co-Design

    … but also are capable of implementing complex computations. The use of these devices in multi-FPGA Custom Computing Machines (CCMs) has provided the potential to execute large sections of programs entirely in custom hardware which can provide a substantial speedup over execution in a …

    vt Repository record for Dataflow Analysis and Optimization of High Level Language Code for Hardware-Software Co-Design (opens in a new tab)

  9. A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes

    Hardware-software co-design techniques are very suitable to develop the next generation of sensornet applications, which have high computational demands. By making use of a low power FPGA, the peak computational performance of a sensor node can be improved without significant degradation of the …

    vt Repository record for A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes (opens in a new tab)

  10. Modeling and Synthesis with SystemC

    With the increasing complexity of Application Specific Integrated Circuits (ASICs), System-On-a-Chip (SoC) design seems to be the current chip design paradigm. Unlike ASICs, SoCs are a potpourri of diverse components, including general-purpose or special-purpose processors. Designing and testing …

    vt Repository record for Modeling and Synthesis with SystemC (opens in a new tab)

  11. Hardware Memory Compression for Large-scale Systems

    Memory has become an increasingly costly resource for both users and service providers, while also contributing significantly to global energy consumption and environmental impact. Memory compression offers a promising solution to mitigate these costs, as memory values exhibit an average …

    vt Repository record for Hardware Memory Compression for Large-scale Systems (opens in a new tab)

  12. Toward Integrating Intelligence Into Everything Around Us

    … of ambient intelligence promises a world where computational capabilities seamlessly integrate into everyday objects and environments, creating systems that sense, learn, and adapt to human needs while remaining invisible to users. Despite significant advances in miniaturization and low-power …

    maryland Repository record for Toward Integrating Intelligence Into Everything Around Us (opens in a new tab)

  13. Execution model and optimizing compilation for execution migration

    Although systems with hardware support for fine-grained execution migration are becoming a reality, no concrete execution model or compiler exist for these machines. This limits the complexity of software that can be written for these machines, and therefore also the scope of studies for which …

    mit Repository record for Execution model and optimizing compilation for execution migration (opens in a new tab)

  14. A Filtered Multitone (FMT) Implementation with Custom Instructions on an Altera FPGA

    … radio frequencies are running out. However, according to a report from the Federal Communications Commission (FCC) in 2002, a different story was told : At any given time and location, much of the prized spectrum lies idle. At the same time, FCC revealed the fact that, in many bands, spectrum …

    vt Repository record for A Filtered Multitone (FMT) Implementation with Custom Instructions on an Altera FPGA (opens in a new tab)

  15. Model based approach to Hardware/ Software Partitioning of SOC Designs

    … a paradigm shift from the traditional system design model to System-On-Chip (SOC) design, the design of custom hardware, embedded processors and associated software have become very tightly coupled. Any change in the implementation of one of the components affects the design of other …

    vt Repository record for Model based approach to Hardware/ Software Partitioning of SOC Designs (opens in a new tab)

  16. Laboratory implementation of unified power flow controller hardware-in-loop simulation

    <p>"One of the most promising network controllers for the bulk power system is the family of power electronics-based controllers, known as "flexible AC transmission system" (FACTS) devices. FACTS devices work by modifying power flow in individual lines of the power grid, maintaining voltage …

    must-thes Repository record for Laboratory implementation of unified power flow controller hardware-in-loop simulation (opens in a new tab)

  17. Towards Zero Trust Network Security via Programmable Data Planes

    … eliminates this ambient trust and requires consistent verification of every access request with the least privileges granted. However, existing network-level and host-level defenses operate in isolation, limiting their ability to correlate inter-host and intra-host activities and thereby …

    vt Repository record for Towards Zero Trust Network Security via Programmable Data Planes (opens in a new tab)

  18. Heterogeneous multiprocessor pipeline design for H.264 video encoder

    … researched for the implementation of video coding applications due to its ability to process data in parallel, its flexibility, high performance, and low cost. However, in recent times, with the release of more complex video coding standards as well as the requirement to transfer high …

    unsw Repository record for Heterogeneous multiprocessor pipeline design for H.264 video encoder (opens in a new tab)

  19. Practical processing and acceleration of graph neural networks

    … uniform structure, such as graphs. Graphs, consisting of a set of nodes, and a set of edges defining relations between the nodes, offer tremendous flexibility for modelling. As a result, we see these models applied to problems ranging from code analysis to recommender systems to drug …

    cambridge Repository record for Practical processing and acceleration of graph neural networks (opens in a new tab)

  20. Circumventing Memory Corruption Mitigations in the Spectre Era: Real-World Attacks and Systematic Analysis of Defenses

    Modern systems are becoming increasingly complex, exposing a large attack surface with vulnerabilities in both software and hardware. In the software layer, memory corruption vulnerabilities can be exploited by attackers to alter the behavior or take full control of a victim program. In the …

    mit Repository record for Circumventing Memory Corruption Mitigations in the Spectre Era: Real-World Attacks and Systematic Analysis of Defenses (opens in a new tab)

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