Global ETD Search

Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.

Results

Showing 1 to 10 of 10 for “"global routing"”.

  1. Performance-driven chip floorplanning and global routing

    … performance-driven chip floorplanning and global routing problems in physical VLSI design are presented. Interconnection delays are estimated and directly incorporated into the problem formulations. A timing analysis provides timing information consisting of a set of potentially critical …

    uiuc Repository record for Performance-driven chip floorplanning and global routing (opens in a new tab)

  2. Floor Planning and Global Routing in an Automated Chip Design System

    In this thesis, a systematic approach has been taken to generating either a slicing or non-slicing structure floorplan. For non-slicing structure layout, the system is divided into initial placement, initial floorplan construction and a floorplan packing. A new analytical model is introduced for …

    uiuc Repository record for Floor Planning and Global Routing in an Automated Chip Design System (opens in a new tab)

  3. Parallel algorithms for placement and routing in VLSI design

    … synthesis tasks, standard cell placement and global routing.

    uiuc Repository record for Parallel algorithms for placement and routing in VLSI design (opens in a new tab)

  4. Optimization of micro-coaxial wire routing in complex microelectronic systems

    In this thesis, we explore wire routing strategies for new paradigms in chip design. Where current chip design techniques involve multi-layered techniques to prevent wire crossings and electrical interference, we work with new technology that utilizes coaxial wires, allowing the construction of …

    mit Repository record for Optimization of micro-coaxial wire routing in complex microelectronic systems (opens in a new tab)

  5. Automatic layout synthesis for high-performance full custom VLSI chips

    … leaf cell construction, partitioning, placement, global routing, detailed routing and transistor/gate sizing, are addressed in our synthesis system. All necessary leaf cells are individually synthesized with customized transistor sizes before placement and tuned after detailed routing. We …

    uiuc Repository record for Automatic layout synthesis for high-performance full custom VLSI chips (opens in a new tab)

  6. Towards Data-Driven Internet Routing Security

    … The Border Gateway Protocol (BGP), the defacto global routing protocol, was not designed to cope with untrustworthy parties, making BGP vulnerable to misconfigurations and attacks from anywhere in the network. Recently, unintended large-scale misconfigurations caused significant amount of …

    mit Repository record for Towards Data-Driven Internet Routing Security (opens in a new tab)

  7. A Design Methodology for Creating Programmable Logic-based Real-time Image Processing Hardware

    … for verification. The circuit partitioning and global routing programs of the TRAVERSE development system software enable automated translation of image processing designs into the resources of multiple FPGA chips in the hardware architecture. In a broad sense, the individual contributions of …

    vt Repository record for A Design Methodology for Creating Programmable Logic-based Real-time Image Processing Hardware (opens in a new tab)

  8. Enhancing network robustness using software-defined networking

    … for example, adapting to network changes, routing traffic bypassing malfunction devices, dropping malicious flows, etc. However, as SDN is rapidly proceeding from vision to reality, the SDN architecture itself might be exposed to some robustness threats. Especially, the SDN control plane is …

    ksu Repository record for Enhancing network robustness using software-defined networking (opens in a new tab)

  9. Layering principles for wireless networks

    … wireline networks is the near optimality of routing (flow) for multiple-unicast traffic: the min-cut upper bound is within a logarithmic factor of the number of sources of the max-flow. This establishes the approximate capacity of multiple-unicast in wireline networks. In this thesis, we …

    uiuc Repository record for Layering principles for wireless networks (opens in a new tab)