Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 50 for “"gate oxide"”.
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Degradation and Breakdown of Ultrathin Gate Oxide
For ultrathin oxides, a new type of failure mode, soft breakdown, has been observed. The characteristics of this kind of failure are often identified by a large increase of gate signal noise level. It has been proposed that there is a threshold power that divides soft and hard breakdown. In this …
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Gate-Oxide-Short Defect Analysis and Fault Modeling Based on FinFET's 3D Structure
… nature in the complex 3D structure of FinFET. Gate-Oxide-Short (GOS) is one of the dominant defects, which has significant impact on circuit reliability. It is the most complex to analyze and difficult to accurately model true behavior of the defective device.This thesis presents a novel …
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STUDY AND CHARACTERIZATION OF INNOVATIVE CLEANING METHODS IN MICROELECTRONICS
… the electronic devices heart, such as Silicon/Gate Oxide interface, in the context of the technological development marked by the "More than Moore" law. As object of this study, one of the most used technologies in the semiconductor industry was used, namely the BCD8, a BCD technology owned by …
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GATE DIELECTRIC BREAKDOWN PHYSICAL ANALYSIS AND STUDIES -2D MODELING OF BREAKDOWN THERMAL EFFECT
Ultra thin gate oxide reliability has been an important aspect in the sub-micron fabrication process. Structural deformation at the gate oxide is indeed important to understand the soft breakdown (SBD) and hard breakdown (HBD) mechanisms of a narrow channel MOSFET. During HBD or under favorable …
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Full chip modeling for predictive simulation of charged device model electrostatic discharge events
… ESD induced failures to become more prominent. Gate oxide failure is the primary signature of CDM ESD. During CDM, the IC is the source as well as the path for the static charge. Therefore, it is important to include the circuit elements representing the package, ESD circuits and the silicon …
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Investigations of the Electric Field Dependencies of the Generation Rates of Oxide and Interface Traps on Silicon
… transistor (BIMOS) is employed to investigate the electric field dependencies of the oxide and interface trap generation and charging on oxidized silicon film on silicon. The substrate emitter/base junction is forward-biased to independently control the current injected into the gate oxide …
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Study Of Oxide Breakdown, Hot Carrier And Nbti Effects On Mos Device And Circuit Reliability
… (HC) effect becomes more significant. When the oxide is scaled down to less than 3 nm, gate oxide breakdown (BD) often takes place. As a result, oxide trapping and interface generation cause long term performance drift and related reliability problems in devices and circuits. The RF front-end …
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The effects of strain on carrier transport in thin and ultra-thin SOI MOSFETs
… geometries such as fully-depleted SOI and double-gate devices are attractive because they can offer superior scaling properties compared to bulk and thick-body SOI devices. The electrostatics of a MOSFET limit how short of a gate length can be achieved before the gate loses control over the …
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A Sub-0.1-Micron PtSi Schottky Source/drain MOSFET
… lightly doped silicon substrates, 19-A to 34-A gate oxide, $\sim$0.05-$\mu$um gate lithography, 100-A sidewall oxides, self-aligned PtSi, and no intentional doping. The thin gate and sidewall oxides enable high field emission currents at low voltages. These devices exhibit on-state currents of …
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Alternative passivation for silicon (100), environmentally benign manufacturing, and cooperative strategy in semiconductor industry
… industrial practice. In addition, a preliminary gate oxide test demonstrated that this methoxy terminated silicon (MeO-Si) yielded a thinner ultra thin gate oxide than those wafers cleaned by IBM's conventional RCA and dilute hydrofluoric acid last clean without compromising its reliability. …
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In-situ impedance characterization for assessing SiC MOSFETs reliability
… confirm that on-state resistance correlates with gate-oxide degradation, while bond-wire lift-off leads to a measurable increase in package inductance. The circuit is thus capable of simultaneously tracking both degradation modes. Its performance is validated through extensive experimental setups …
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Study Of Nanoscale Cmos Device And Circuit Reliability
… of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance …
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Two-Dimensional Analysis of Narrow Gate Effects in Micron and Submicron Mosfets (Device Simulation, Modeling)
… due to the geometry effects in narrow gate MOSFETs, such as threshold voltage shift and subthreshold characteristics, are important factors in designing next generation MOS-VLSI circuits. It is well known that numerical methods, using the exact 2-D solutions of the transport equation …
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Device and Circuit Level EMI Induced Vulnerability: Modeling and Experiments
… integrated circuits (ICs). Metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the ICs may be disrupted under EMI conditions due to transient voltage-current surges, and their internal states may change undesirably. In this work, the vulnerabilities of silicon MOSFETs …
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InGaAs/GaAsSb quantum-well Tunnel-FETs for ultra-low power applications
… (TFET), where carrier injection is determined by gate-controlled tunneling from the source to the channel, has been attractive as one of the promising candidates for future ultra-low power applications. In this thesis, inline-TFETs with tunneling direction aligned to the gate electric field are …
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Characterization, Reliability and Packaging for 300 °C MOSFET
… there are reliability issues relating to the gate oxide region of the MOSFET, which is exacerbated through high temperature conditions. In this thesis, high temperature effects on current-generation SiC MOSFETs are studied and analyzed. To achieve this, a high temperature package is created to …
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Assessing Approximate Arithmetic Designs in the presence of Process Variations and Voltage Scaling
… units, other seeds such as basic logic gates with limited logic space were used to develop completely new multi-bit approximate adders with good fitness levels. iii The effect of process variation was also calculated. As the number of transistors is reduced, the distribution of the …
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Negative bias temperature instability (NBTI) experiment
… characteristics of Complementary Metal Oxide Semiconductor (CMOS) devices, and tends to have a stronger effect on p-channel devices. This instability is observed with an applied "on" biasing during normal operation and can be accelerated with thermal stress. A normal applied electrical …
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Full-band Monte Carlo simulation of hot electrons in scaled silicon devices
… of the electrons, and the drain, substrate, and gate currents. The locations of impact ionization events and injection into the gate oxide are examined. It is shown that simpler models cannot adequately predict hot carrier behavior at the channel lengths studied (below 0.3 $\mu$m) and that …
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Towards in-situ device fabrication : electrostatic lithography and nanowire field effect devices
… ranged from carbon black, gold, silver, iron oxide, aluminum oxide and silicon oxide. Multiple nanoparticle delivery methods were employed including immersion in a nanoparticle solution, exposure to a nanoparticle aerosol, electrosprayed nanoparticles and in-situ delivery of nanoparticles. The …
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