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Showing 1 to 20 of 20 for “"functional verification"”.

  1. A meta-language for functional verification

    … the search for simulation traces toward reaching verification closure, and that of coordinating the search for a proof within a theorem prover. The programmatic coordination of simulation is difficult with existing tools for digital circuit verification because stimuli generation, simulation …

    uiuc Repository record for A meta-language for functional verification (opens in a new tab)

  2. Functional verification and timing analysis of large digital emitter-coupled logic circuits including voltage regulators

    This thesis describes the algorithms implemented in a new digital emitter-coupled logic (ECL) simulation tool called iECLSIM (Illinois ECL SIMulator). From a transistor-level description, we first partition the circuit into blocks at base nodes and voltage source nodes to exploit latency in time …

    uiuc Repository record for Functional verification and timing analysis of large digital emitter-coupled logic circuits including voltage regulators (opens in a new tab)

  3. Design Verification for Sequential Systems at Various Abstraction Levels

    … ever increasing complexity of digital systems, functional verification has become a daunting task to circuit designers. Functional verification alone often surpasses 70% of the total development cost and the situation has been projected to continue to worsen. The most critical limitations of …

    vt Repository record for Design Verification for Sequential Systems at Various Abstraction Levels (opens in a new tab)

  4. Verification and Configuration of a Run-Time Reconfigurable Custom Computing Integrated Circuit for DSP Applications

    … of the Colt chip is architectural justification, functional verification, and configurability. This thesis explores verification of the Colt chip at various levels of development including mapping arithmetic computations and DSP algorithms that the Colt architecture was designed to solve.

    vt Repository record for Verification and Configuration of a Run-Time Reconfigurable Custom Computing Integrated Circuit for DSP Applications (opens in a new tab)

  5. 3D-SoftChip: A novel 3D vertically integrated adaptive computing system [thesis]

    … along with high-level system modeling and functional verification in the early design stage using SystemC.

    edithcowan Repository record for 3D-SoftChip: A novel 3D vertically integrated adaptive computing system [thesis] (opens in a new tab)

  6. Design and in vivo verification of a stress radiography device towards it's suitability for multi-ligament laxity measurements

    … degrees of knee joint flexion. The in vitro functional verification of the device was limited to (according to scope) a single cadaver trial; to validate functionality, structural integrity, usability as well as demonstrate the Laxmeter concept prior to a prospective full clinical trial. The …

    cape-town Repository record for Design and in vivo verification of a stress radiography device towards it's suitability for multi-ligament laxity measurements (opens in a new tab)

  7. Easy-filter: A Design, Verification, and Validation Tool for Finite Impulse Response (FIR) Filter

    … for the short time-to-market requirement, functional verification becomes the primary challenge in the hardware design development project. The essential parts to verify any systems are design code and testbench code. However, it is very labor-intensive to write these codes and prone to …

    texas-state Repository record for Easy-filter: A Design, Verification, and Validation Tool for Finite Impulse Response (FIR) Filter (opens in a new tab)

  8. Optimizing Verification of RTL Designs Using Reinforcement Learning Methods

    … systems work first-time is paramount. Digital verification paradigms and techniques have therefore also evolved in parallel with the scale integration evolution. Today the most prevalent paradigm for digital designs modelled at the Register Transfer Logic (RTL) level is the ‘simulation based …

    bielefeld Repository record for Optimizing Verification of RTL Designs Using Reinforcement Learning Methods (opens in a new tab)

  9. Null Convention Logic applications of asynchronous design in nanotechnology and cryptographic security

    … S-Box for Advanced Encryption Standard (AES). Functional verification has been done using Modelsim and Field-Programmable Gate Array (FPGA). 2) Implemented two different power analysis attacks on both NCL S-Box and conventional synchronous S-Box. 3) Developed a novel approach based on …

    must-thes Repository record for Null Convention Logic applications of asynchronous design in nanotechnology and cryptographic security (opens in a new tab)

  10. Contributions to the advance of the integration density of CubeSats

    … subsystems to form a highly integrated, multi-functional solar panel. Eligible components are usually allocated to the communication system, the electric power system, or the attitude determination and control system. In a joint research project, development, optimization, and miniaturization …

    tu-berlin Repository record for Contributions to the advance of the integration density of CubeSats (opens in a new tab)

  11. Uncovering Biophysical Determinants Of Oxidoreductase Function Through De Novo Protein Design

    … from one substrate to another. Comprising the functional cores of photosynthetic, chemosynthetic, and cellular respiratory machinery, “redox proteins” and the catalysis they enable form the foundation biological energy transduction. Mastering the mechanisms by which these enzymes work is the …

    penn Repository record for Uncovering Biophysical Determinants Of Oxidoreductase Function Through De Novo Protein Design (opens in a new tab)

  12. Mining constraints for Testing and Verification

    … challenges to the digital hardware design. Functional verification has become one of the most expensive and time-consuming components of the current product development cycle. Today, design verification alone often surpasses 70% of the total development cost and the situation has been …

    vt Repository record for Mining constraints for Testing and Verification (opens in a new tab)

  13. Exploring Temporal and Spatial Correlations on Circuit Variables for Enhancing Simulation-based Test Generation

    … of current circuit designs have made testing and verification major bottlenecks in the design flow of VLSI (Very Large Scale Integrated) circuits. Statistics show that more than 70% of the design effort can be spent on functional verification and manufacturing testing. This percentage is expected …

    vt Repository record for Exploring Temporal and Spatial Correlations on Circuit Variables for Enhancing Simulation-based Test Generation (opens in a new tab)

  14. Mining Multinode Constraints and Complex Boolean Expressions for Sequential Equivalence Checking

    … poses several challenges to the digital hardware verification. Functional verification has become the most expensive and time-consuming task in the overall product development cycle. Almost 70\% of the total verification time is being consumed by design verification and it is projected to worsen …

    vt Repository record for Mining Multinode Constraints and Complex Boolean Expressions for Sequential Equivalence Checking (opens in a new tab)

  15. Proteomic analysis of genetically stratified grade-I meningioma

    … in mutant subtypes. Further validation and functional verification of potential candidates will allow us to identify potential drug targets/biomarkers for benign meningiomas.

    plymouth Repository record for Proteomic analysis of genetically stratified grade-I meningioma (opens in a new tab)

  16. Design and development of an adaptive external bone fracture fixation system

    … deformities via controlled shape change. The functional verification of the device was limited to (according to the scope) stress testing. The proposed device consists of hinge systems capable of allowing for full assembly expansion to permit quick installation for various injury structures or …

    cape-town Repository record for Design and development of an adaptive external bone fracture fixation system (opens in a new tab)

  17. High Quality Test Generation at the Register Transfer Level

    … tests applicable for both structural and functional tests. These testing methods allow for significantly faster test generation for functional tests as well as providing high levels of fault coverage during structural test, typically outperforming previous state of the art methods. First, …

    vt Repository record for High Quality Test Generation at the Register Transfer Level (opens in a new tab)

  18. Functional and physiological discovery in the mannonate dehydratase subgroup of the enolase superfamily

    … databases. This dissertation details the functional and physiological characterization of the mannonate dehydratase subgroup (ManD) of the enolase superfamily (ENS). The outcome affirms the dangers of homology-based annotations while discovering novel metabolic pathways. Furthermore, the …

    uiuc Repository record for Functional and physiological discovery in the mannonate dehydratase subgroup of the enolase superfamily (opens in a new tab)

  19. Sequential Equivalence Checking with Efficient Filtering Strategies for Inductive Invariants

    … Due to the limited capability of sequential verification tools, aggressive sequential optimization is shunned nowadays as there is no efficient way to prove the preservation of equivalence after optimization. Due to the fact that the number of transistors fitting on single fixed-size die …

    vt Repository record for Sequential Equivalence Checking with Efficient Filtering Strategies for Inductive Invariants (opens in a new tab)

  20. A domain specific language for facilitating automatic parallelization and placement of SDR patterns into heterogeneous computing architectures

    … testing using root-mean square error, and functional verification of DSP using two-dimensional graphics plotting for radar and real-time spectral analysis plots.

    cape-town Repository record for A domain specific language for facilitating automatic parallelization and placement of SDR patterns into heterogeneous computing architectures (opens in a new tab)