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Showing 1 to 5 of 5 for “"fractional-N PLL"”.
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Fractional-N PLL-Based Waveform Synthesis for FMCW SAR
… is done by considering the phase-locked loop (PLL) synthesiser employed and waveforms, thereof, in terms of dynamic response characteristics and frequency response characteristics. The dynamic response component entails studying parameters which include the modulation period, modulation …
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Energy-efficient wireline transceivers
… (CDR) using phase-rotating phase-locked loop (PRPLL) to conduct phase control so as to break several fundamental trade-offs in conventional receivers; (2) a 4-10.5Gb/s continuous-rate CDR with novel frequency acquisition scheme based on bang-bang phase detector (BBPD) and a ring oscillator-based …
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Clock multiplication techniques for high-speed I/Os
… clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock multiplication techniques have …
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Digital enhancement techniques for fractional-N frequency synthesizers
… In the first part of this work, a digital fractional-N phase locked loop (FNPLL) that employs a high resolution time-to-digital converter (TDC) and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time …
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Design of energy efficient high speed I/O interfaces
The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.