Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 155 for “"formal verification"”.
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FORMAL VERIFICATION-BASED PROGRAM REPAIR
Automated program repair has been an active research field in software engineering in the last decade. It aims to help developers automatically localize and fix program bugs, consequently reducing debugging efforts. Automated repair tools have been incorporated into continuous integration and code …
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Formal verification-driven parallelisation synthesis
… one. This dissertation presents two novel formal verification-based methods for safely transforming a sequential program into a concurrent one. The first method---an instance of proof-directed synthesis---takes as the input a sequential program and its safety proof, as well as annotations …
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Abstraction Guided Semi-formal Verification
Abstraction-guided simulation is a promising semi-formal framework for design validation in which an abstract model of the design is used to guide a logic simulator towards a target property. However, key issues still need to be addressed before this framework can truly deliver on it's promise. …
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Formal Verification Techniques for Reversible Circuits
As the number of transistors per unit chip area increases, the power dissipation of the chip becomes a bottleneck. New nano-technology materials have been proposed as viable alternatives to CMOS to tackle area and power issues. The power consumption can be minimized by the use of reversible logic …
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Strategies for SAT-Based Formal Verification
Verification of digital hardware designs is becoming an increasingly complex task as the designs are incorporating more functionality, becoming complex and growing larger in size. Today, verification remains a bottleneck in meeting time-to-market requirements and consumes more than 70% of the …
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Formal verification of distributed deadlock detection algorithms
… detection has undergone extensive study. Formal verification of deadlock detection algorithms in distributed systems is an area of research that has largely been ignored. Instead, most proposed distributed deadlock detection algorithms have used informal or intuitive arguments, simulation …
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An Effective SMT Engine for Formal Verification
Formal methods are becoming increasingly important for debugging and verifying hardware and software systems, whose current complexity makes the traditional approaches based on testing increasingly-less adequate. One of the most promising research directions in formal verification is based on the …
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On the formal verification of ATM switches
… designs, there has been a surge of interest in formal verification, in which a mathematical model of the design is proved to satisfy a precise specification. Model Checking and Equivalence Checking , which have the advantage of automatic verification, are two main formal verification techniques …
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A formal verification assistant for TROMLAB environment
Formal specifications have become a strong basis in the field of safety critical systems development. Safety, liveness and time bounded properties are characteristics of such systems where the need to secure their adequate implementation is very high. Formal verification of such properties is the …
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Formal verification of biologically inspired computing models
… and computing power. This thesis discusses the formal verification of cP systems. cP systems support labelled multiset-based terms and generic rewriting rules. To apply a rule, variable terms in its lhs (left-hand-side) and promoters need to be unified against system terms. Although several …
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Formal verification of TCP and T/TCP
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.
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Formal verification of safety-critical hybrid systems
This thesis investigates how the formal modeling and verification techniques of computer science can be used for the analysis of hybrid systems [7,14,22,37] - systems involving both discrete and continuous behavior. The motivation behind such research lies in the inherent similarity of the …
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Exploring Constraint Satisfiability Techniques in Formal Verification
… promising application of this MAX-SAT solver in formal verification.
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Using Live Sequence Chart Specifications for Formal Verification
<p>Formal methods play an important part in the development as well as testing stages of software and hardware systems. A significant and often overlooked part of the process is the development of specifications and correctness requirements for the system under test. Traditionally, English has been …
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Formal verification of cryptographic protocols with automated reasoning
… security properties. This thesis advances verification techniques for cryptographic protocols using formal methods with an emphasis on automation. The key contributions are threefold. Firstly, a definition of election verifability for electronic voting protocols is presented; secondly, a …
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Formal verification of simulations between I/O automata
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
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Formal Verification of an Implementation of the Roughtime Server
Formal verification has been used in the past few decades to prove correctness of programs. This thesis provides a verification of a simpler implementation of Roughtime [1], a protocol that consists of securely querying the current time via a client-server interaction. The tool that was used is …
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Enhancing SAT-based Formal Verification Methods using Global Learning
… intricate systems. The two most widely used formal methods for design verification are Equivalence Checking and Model Checking. Equivalence Checking requires that the implementation circuit should be exactly equivalent to the specification circuit (golden model). In other words, for each …
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Techniques for formal verification of concurrent and distributed program traces
… in concurrent and distributed programs include formal methods and testing. This dissertation presents an approach toward combining formal methods and testing, while avoiding the complexity of model checking or theorem proving and the pitfalls of ad hoc testing. Our technique enables efficient …
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Safety cases for the formal verification of automatically generated code
… that their output is correct or even safe. Formal methods which are based on mathematically-based techniques have been proposed as a means to improve software quality by providing formal safety proofs as explicit evidence for the assurance claims. However, the proofs are often complex and …
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