Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 19 of 19 for “"floating-point arithmetic"”.
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On synthesis and optimization of floating point units
… level design decisions on the performance, of floating point arithmetic units. By modeling with VHDL and using design synthesis techniques, different architectures of floating point adders, multipliers and multiply-accumulate fused units, are compared using different technologies and cell …
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Pipelining Of Double Precision Floating Point Division And Square Root Operations On Field-programmable Gate Arrays
… These algorithms use double precision floating point arithmetic operations. While most DSP applications can be executed on DSP processors, the DSP numerical requirements of these new space applications surpass by far the numerical capabilities of many current DSP processors. Since the …
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ΜΕΛΕΤΗ ΤΗΣ ΥΠΟΛΟΓΙΣΤΙΚΗΣ ΠΟΛΥΠΛΟΚΟΤΗΤΑΣ ΑΛΓΟΡΙΘΜΩΝ ΤΗΣ ΨΗΦΙΑΚΗΣ ΕΠΕΞΕΡΓΑΣΙΑΣ ΠΟΛΥΔΙΑΣΤΑΤΩΝ ΣΗΜΑΤΩΝ
… ARE PRESENTED. FINALLY THE ERROR ANALYSIS IN FLOATING POINT ARITHMETIC OF THE RECTANGULAR TRANSFORM AND THE MULTIDIMENSIONAL DFTS IS PRESENTED.
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An image based colorimetric technique for portable blood gas analysis
… The colorimetric algorithm is implemented using floating point arithmetic architectures for high accuracy with an emphasis on low power consumption and area.
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Implementation of a 2-D fast Fourier transform on an FPGA-based computing platform
… of a 2-D FFT requires O(N²log₂N ) complex floating point arithmetic operations for an NxN image. By implementing the FFT algorithm on a custom computing machine (CCM) called Splash-2, a computation speed of at least 180 Mflops and a speed-up of 23 times over a SPARC-10 workstation is …
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A design of floating point FFT using Genesil Silicon Compiler.
The hardware of floating-point MULTIPLY, ADD, and SUBTRACT units are designed to support the multiplication, addition, and subtraction operation necessary in the Fast Fourier Transform (FFT). In this thesis, the IEEE floating-point standard is adopted and scaled down to 16 bits, but the exponent is …
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Robust evaluation of differential geometry properties using interval arithmetic techniques
… equation (ODE) system solver based on interval arithmetic. Iso-contouring of curvature of a Bezier surface patch. computation of curvature lines of a Bezier surface patch and computation of geodesics of a Bezier surface patch are computed by the Validated Numerical Ordinary Differential …
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Analysis and Evaluation of the Family of Sign Adaptive Algorithms
… by the author were analyzed and evaluated for floating-point arithmetic operations. These four algorithms include Sign Regressor Least Mean Fourth (SRLMF), Sign Regressor Least Mean Mixed-Norm (SRLMMN), Normalized Sign Regressor Least Mean Fourth (NSRLMF), and Normalized Sign Regressor Least …
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Faster fully polynomial approximation schemes for Knapsack problems
… for knapsack problems. We propose the use of floating point arithmetic rather than the use of geometric rounding in order to simplify analysis. Given a knapsack problem that yield an ... -optimal solution for disjoint subsets S and T of decision variables, we show how to attain ... -optimal …
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Stereo vision based on compressed feature correlation and graph cut
… eliminating time consuming multiplication and floating point arithmetic. Unlike the traditional fixed window sorting scheme, adaptive correlation window positioning is implemented by dynamically placing strong features at the center of each correlation window. A confidence measure is developed …
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Low-complexity approximations for discrete transforms : design, fast algorithms, image coding, and use as a tool in statistical inference
… can be a solution for the reduction of arithmetic operations necessary for computing the transforms. However, it is still necessary to deal with the floating-point arithmetic. Thus, several low-complexity transform approximations have been developed, as a low-cost alternative for …
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Pseudo-Round: An Alternative Approach for Floating-Point Representation
No abstract prepared.
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Fast and Scalable Architectures and Algorithms for the Computation of the Forward and Inverse Discrete Periodic Radon Transform with Applications to 2D Convolutions and Cross-Correlations
… increased hardware complexity due the need for floating point arithmetic implementations. An alternative implementation of the DRT is through the use of the Discrete Periodic Radon Transform (DPRT). The DPRT also exhibits discrete properties of the continuous-space Radon Transform, including the …
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Software-defined pulse-doppler radar signal processing on graphics processors
… circuits that typically employ restrictive fixed-point arithmetic. The first stage generally requires FIR filters, correlation, Fourier transforms, and matrix-vector algebra on multi-dimensional data, which provides a range of demanding and interesting computational challenges, and that present …
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Towards Reliable AI via Efficient Verification of Binarized Neural Networks
… input. However, many existing verifiers target floating point networks but, for efficiency reasons, do not exactly model the floating point computation. As a result, they may produce incorrect results due to floating point error. In this context, Binarized Neural Networks (BNNs) are attractive …
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Design and implementation of a floating point unit for rigel, a massively parallel accelerator
Scientific applications rely heavily on floating point data types. Floating point operations are complex and require complicated hardware that is both area and power intensive. The emergence of massively parallel architectures like Rigel creates new challenges and poses new questions with respect …
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New techniques for the Reliability Evaluation of AI-oriented Hardware Accelerators
L'abstract è presente nell'allegato / the abstract is in the attachment
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Hardware acceleration of Monte Carlo-based simulations
… processors. This Thesis is focused on the last point, the use of FPGAs to accelerate computationally intensive applications. The use of FPGAs for hardware acceleration is an active research field. However, there are still several challenges concerning the use of FPGAs as accelerators: • …