Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 127 for “"floating point"”.
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Floating-Point Analog-to-Digital Converter
… at high data rates, the approach of using a floating-point analog-to-digital converter (FP-ADC) has been investigated. This approach de-links the dynamic range with the resolution, and a very wide dynamic range can be achieved by an ADC with a moderate resolution. The solution for an FP-ADC …
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Software floating-point computation on parallel mahcines
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.
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On synthesis and optimization of floating point units
… level design decisions on the performance, of floating point arithmetic units. By modeling with VHDL and using design synthesis techniques, different architectures of floating point adders, multipliers and multiply-accumulate fused units, are compared using different technologies and cell …
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On low power floating point data path architectures
… for the implementation of low power floating point units--adders, multipliers and multiply-accumulators. Philosophically, higher level design starts with the characterization of the behavior of the system under consideration. In this work, the design philosophy of floating point …
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Low-power single-precision IEEE Floating-point unit
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
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Pseudo-Round: An Alternative Approach for Floating-Point Representation
No abstract prepared.
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Higher Radix Floating-Point Representations for FPGA-Based Arithmetic
… are increasingly being used for high-throughput floating-point computation. It is forecasted that by 2009, FPGAs will provide an order of magnitude greater sustained floating-point throughput than conventional processors. FPGA implementations of floating-point operators have historically been …
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Servo compensation using a floating point digital signal processor
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics, 1989.
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A design of floating point FFT using Genesil Silicon Compiler.
The hardware of floating-point MULTIPLY, ADD, and SUBTRACT units are designed to support the multiplication, addition, and subtraction operation necessary in the Fast Fourier Transform (FFT). In this thesis, the IEEE floating-point standard is adopted and scaled down to 16 bits, but the exponent is …
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Floating-point unit (FPU) designs with nano-electromechanical (NEM) relays
… CMOS despite their slow actuation times. The floating-point unit (FPU) is the most complex arithmetic unit in a computational system. This thesis investigates if the energy-efficiency promise of NEM relays demonstrated before on smaller circuit blocks holds for complex computational structures …
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Analysis of performance/accuracy tradeoffs for floating point applications on GPUS
Floating-point computations produce approximate results, which can lead to inaccuracy problems. Existing work addresses two issues: first, the design of high precision floatingpoint representations; second, the study of methods to trade-off accuracy and performance of serial CPU applications. …
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Floating point multiply/add unit for the M-machine node processor
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.
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Design of an IEEE double precision floating-point adder/subtractor in GaAs technology
This project aims to produce a 64-bit floating-point double precision adder/subtractor of a Solid Modelling accelerator in Gallium Arsenide technology, which is used to reduce computational time and to increase accuracy of algorithms. Addition is the most fundamental and the simplest operation in …
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Static analysis for detecting and avoiding floating-point run-time errors in logic programs
… is to provide techniques for the abstraction of floating-point expressions into the polyhedra domain as well as into the finite powerset of polyhedra domain. Moreover, this thesis aims at presenting a forward and a backward analysis for the detection and inference of floating-point errors such as …
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Design and implementation of a floating point unit for rigel, a massively parallel accelerator
Scientific applications rely heavily on floating point data types. Floating point operations are complex and require complicated hardware that is both area and power intensive. The emergence of massively parallel architectures like Rigel creates new challenges and poses new questions with respect …
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A hierarchical verification of the IEEE-754 table-driven floating-point exponential function using HOL
The IEEE-754 floating-point standard, used in nearly all floating-point applications, is considered one of the most important standards. Deep datapath and algorithm complexity have made the verification of such floating-point units a very hard task. Most simulation and reachability analysis …
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Pipelining Of Double Precision Floating Point Division And Square Root Operations On Field-programmable Gate Arrays
… These algorithms use double precision floating point arithmetic operations. While most DSP applications can be executed on DSP processors, the DSP numerical requirements of these new space applications surpass by far the numerical capabilities of many current DSP processors. Since the …
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