Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 12 of 12 for “"fault modeling"”.
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Behavioral delay fault modeling and test generation
… operation of VLSI devices has increased, delay fault testing has become a more important factor in VLSI testing. Due to the large number of gates in a VLSI circuit, the gate level test generation methodologies may become infeasible for delay test generation. In this work, a new behavioral delay …
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Micro-operation perturbations in chip level fault modeling
… is the best micro-operation perturbation for modeling fault at the chip level? In this thesis, an automatic evaluation system is developed to determine the best micro-operation perturbation. The measure used is the gate level stuck-at fault coverage achieved by the tests derived to cover the …
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Functional fault modeling and test vector development for VLSI systems
The attempts at classification of functional faults in VLSI chips have not been very successful in the past. The problem is blown out of proportions because methods used for testing have not evolved at the same pace as the technology. The fault-models proposed for LSI systems are no longer capable …
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Gate-Oxide-Short Defect Analysis and Fault Modeling Based on FinFET's 3D Structure
… of defects and dominance of others, accurate modeling of the defects and generation of reliable fault models are essential to create realistic set of test vectors to detect the defects.Automatic test pattern generation (ATPG) algorithms use traditional fault models that primarily capture the …
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Fault Injection Attacks on RSA and CSIDH
Fault injection attacks are a powerful technique that intentionally induces faults during computations to leak secret information. This thesis studies the fault injection attack techniques. The thesis first categorizes various fault attack methods by fault model and fault analysis and gives …
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From TPU to QPU: Bridging Fidelity Gaps Across Next-Generation Computing Systems
… This methodology utilizes detailed circuit-level fault models, exposing how hardware defects propagate to application-level outputs. The approach establishes structured fault characterization that improves application-level robustness without excessive hardware redundancy. Building on insights …
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An innovative fault analysis framework to enhance building operations
… A literature review was conducted for fault modeling and the fault mode and effect analysis (FMEA) applications to the building technology with a conclusion that few FMEA studies were applied in the building Heating, Ventilation, and Air-Conditioning (HVAC) systems. This study aims to …
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Probabilistic design for emerging memory and nanometer-scale logic
… the use of probabilistic methods and models: (1) Modeling and exploiting stochastic behavior in advanced memory technologies; (2) Probabilistic modeling of faults due to on-chip voltage variation. This dissertation first investigates the unique physics-level stochasticity of spin-transfer torque …
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Numerical and Experimental Analysis of the Effect of Faults in Open-Pit Mining Stability
… two main issues in slope stability: 1) effect of faults in the large open pit mines and large rock slopes, and 2) improving stability of tailing dames using Hydro-Jex® technology.Section 1 - Effect of faults in the large open pit mines and large rock slopes: Deep open pit mines and large rock …
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Online Techniques for Enhancing the Diagnosis of Digital Circuits
… most of these activities cater for all possible faults without making any assumptions about the actual defects present in the circuit. As the size of the circuits continues to increase (following the Moore's Law) the size of the test sets is also increasing exponentially. It follows that the cost …
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Detection, diagnosis and modeling of ESD-induced soft failures - a gate-level and mixed-signal approach
… We implemented a mixed-signal-simulation-based fault injection environment and device models to allow ESDs to be injected to target systems. By injecting different types of ESDs into the target system, we, for the first time, identified gate-level bit-flip patterns from a SPICE level …
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Estimating the Dynamic Sensitive Cross Section of an FPGA Design through Fault injection
A fault injection tool has been created to emulate single event upset (SEU) behavior within the configuration memory of an FPGA. This tool is able to rapidly and accurately determine the dynamic sensitive cross section of the configuration memory for a given FPGA design. This tool enables the …