Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 30 for “"equivalence checking"”.
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Equivalence checking of retimed circuits
… thesis addresses the problem of verifying the equivalence of two circuits, one or both of which have undergone register retiming as well as logic resynthesis. The aim of the thesis is to improve the ability of Formality, an equivalence checking tool written at Synopsys, to handle retimed …
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Efficient Equivalence Checking in a Modular Design Environment
… designs to enable the application of the current equivalence checking techniques. We propose an algorithm to compute the steady states of a machine by relaxing the assumption of a designated set of initial states (DIS). This assumption is used in research but is often restrictive in an industrial …
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Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking
… One of the core areas of Verification is Equivalence Checking (EC), which is a special yet independent case of Model Checking (MC). Equivalence Checking aims to prove that two circuits, when fed with the same inputs, produce the exact same outputs. There are broadly two ways to conduct …
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Fast Discovery of Illegal State Cubes for Sequential Equivalence Checking
Sequential Equivalence checking has been and still is a challenging problem. Verifying two circuits that are structurally different but logically the same is very important and has many applications. Critical to the success of sequential equivalence checking is the determination of a sufficient …
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Sequential Equivalence Checking with Efficient Filtering Strategies for Inductive Invariants
… is no efficient way to prove the preservation of equivalence after optimization. Due to the fact that the number of transistors fitting on single fixed-size die increases with Moore's law, the problem gets harder over time and in an exponential rate. It is no surprise that functional verification …
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Mining Multinode Constraints and Complex Boolean Expressions for Sequential Equivalence Checking
… used formal method to perform this process is equivalence checking. The success of combinational equivalence checking (CEC) has contributed to aggressive combinational logic synthesis and optimizations for circuits with millions of logic gates. However, without powerful sequential equivalence …
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Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking
… (IP) using a clever combination of sequential equivalence checking (SEC) and automatic test generation. The use of powerful inductive invariants can prune a large illegal state space, and test generation helps to provide a sensitization path for nodes of interest. Results for a set of …
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Sequential Equivalence Checking of Circuits with Different State Encodings by Pruning Simulation-based Multi-Node Invariants
… that up to 70% of the design effort is spent on checking if the design is functionally correct. One of the core verification tasks is Equivalence Checking (EC), which attempts to check if two structurally different designs are functionally equivalent for all reachable states. Powerful equivalence …
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Mining constraints for Testing and Verification
… used formal methods for design verification are Equivalence Checking and Model Checking. During the design phase, hardware goes through several stages of optimizations for area, speed, power, etc. Determining the functional correctness of the design after each optimization step by means of …
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On the formal verification of ATM switches
… proved to satisfy a precise specification. Model Checking and Equivalence Checking , which have the advantage of automatic verification, are two main formal verification techniques that people are working on. The main problem of model checking and sequential equivalence checking is the state space …
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Modeling and formal verification of a telecom system block using MDGs
… we followed a hierarchical approach for the equivalence checking of the TSB. We first verified that the RTL implementation of each module complies with the specification of its behavioral model. We also succeeded to verify the full RTL implementation of the TSB against its top level …
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Integration of HOL and MDG for hardware verification
… MDG (Multiway Decision Graphs) which supports equivalence checking and model checking. We developed a linkage tool between HOL and MDG which uses the specification and implementation of a circuit written in HOL to automatically generate all required MDG files. It then calls the MDG equivalence …
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Formal Verification Techniques for Reversible Circuits
… Consequently, this demands research in efficient equivalence checking techniques for reversible circuits. This thesis explores the optimization and equivalence checking of reversible circuits. Most of the existing synthesis techniques work in two steps — generate an original, often sub-optimal, …
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Enhancing SAT-based Formal Verification Methods using Global Learning
… used formal methods for design verification are Equivalence Checking and Model Checking. Equivalence Checking requires that the implementation circuit should be exactly equivalent to the specification circuit (golden model). In other words, for each possible input pattern, the implementation …
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Static Learning for Problems in VLSI Test and Verification
… sequentially untestable stuck-at faults, and (2) Equivalence checking of sequential circuits. Additionally, for the dissertation, we define a new concept called multi-cycle path delay faults (M-pdf) for latch based designs with multiple clock domains, and propose an implications-based methodology …
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MSL : a synthesis enabled language for distributed high performance computing implementations
… new analyses in order to support synthesis and equivalence checking for programs written in SPMD-style, as well as empirical evaluations of our new methodology.
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Translation validation for compilation verification
… system are (1) a formal notion of program equivalence, (2) a verification condition generator that generates a relation between program points and variables in the input and output programs, (3) a proof system that accepts the verification conditions, generates a machine-checkable …
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Semantics-based program verification
… analyses: program verification and program equivalence. First, we propose a novel notion of bisimulation, which we call cut-bisimulation, allowing the two programs to semantically synchronize at relevant ""cut"" points, but to evolve independently otherwise. Employing the cut-bisimulation, …
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