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Showing 1 to 9 of 9 for “"dynamic random-access memory (DRAM)"”.

  1. Chemically modified Ta₂O₅ thin films for dynamic random access memory (DRAM) applications

    … the fabrication of a reliable high-density memory device. In the present work, the effects of Al addition on Ta₂O₅ thin films were systematically studied. The structural and electrical properties of these chemically modified thin films were investigated in detail to establish their potential …

    vt Repository record for Chemically modified Ta₂O₅ thin films for dynamic random access memory (DRAM) applications (opens in a new tab)

  2. The SCALE DRAM subsystem

    Dynamic Random Access Memory (DRAM) is consuming an ever-increasing portion of a system's energy budget as advances are made in low-power processors. In order to reduce these energy costs, modern DRAM chips implement low-power operating modes that significantly reduce energy consumption but …

    mit Repository record for The SCALE DRAM subsystem (opens in a new tab)

  3. A strategic and financial analysis of the DRAM industry

    The manufacturing and development of Dynamic Random Access Memory (DRAM) is a large global industry that involves various advanced technologies and significant capital expenditures. The industry has seen tremendous developments over the past few decades allowing for rapidly improving product …

    mit Repository record for A strategic and financial analysis of the DRAM industry (opens in a new tab)

  4. Software-defined Significance-Driven Computing

    … it to operate seamlessly on top of unreliable memory and provide a<br/>user-space interface for memory allocation from the unreliable portion of the physical memory. Having this framework in place<br/>allowed us to identify what we call the refresh-by-access property of applications that use …

    qu-belfast Repository record for Software-defined Significance-Driven Computing (opens in a new tab)

  5. EPITAXIAL SPIN-ORBIT AND MAGNETIC MATERIALS FOR INTEGRATION ONTO A SEMICONDUCTOR PLATFORM

    … historically served as the backbone fordigital memory storage. In recent times, however, charge-based memories, such as flash and dynamic random access memory (DRAM), have become more commonplace. Over the last few decades, advancements in the field of spintronics, which aims to unify usage of …

    cornell Repository record for EPITAXIAL SPIN-ORBIT AND MAGNETIC MATERIALS FOR INTEGRATION ONTO A SEMICONDUCTOR PLATFORM (opens in a new tab)

  6. Configuring In-Memory Caches: From TTL-Aware Sizing to Interval-Based Historical Analysis with HistoChron

    In-memory caches such as Memcached and Redis are crucial for enhancing the performance of distributed systems by significantly reducing query response times. Correctly sizing these caches is critical, especially considering that prominent organizations use terabytes to petabytes of Dynamic Random

    toronto-retro Repository record for Configuring In-Memory Caches: From TTL-Aware Sizing to Interval-Based Historical Analysis with HistoChron (opens in a new tab)

  7. Impact of Lot Dedication on the Performance of the Fab

    … manufacturing line that is used to produce four dynamic random access memory (DRAM) products, requiring approximately 240 stages with 18 photolithography layers, is considered. The problem we propose to investigate can concisely be described as follows: Given a set of products to be processed in …

    vt Repository record for Impact of Lot Dedication on the Performance of the Fab (opens in a new tab)

  8. Refresh reduction in dynamic memories

    … to use a low-leakage technology such as embedded DRAM (eDRAM). Unfortunately, eDRAM, being a dynamic memory, requires periodic refresh, which ends up consuming substantial energy for large last-level caches. In upcoming architectures that stack a processor die and multiple DRAM dies, DRAM dies …

    uiuc Repository record for Refresh reduction in dynamic memories (opens in a new tab)

  9. Next-generation safety-critical systems on multi-core platforms

    … Shared hardware resources like caches, main memory, and I/O buses are all sources of unpredictable timing behavior and temporal dependencies among real-time tasks running in parallel. As a result, certifying systems deployed using multi-core platforms is significantly more challenging …

    uiuc Repository record for Next-generation safety-critical systems on multi-core platforms (opens in a new tab)