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Showing 1 to 4 of 4 for “"dynamic comparator"”.
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Cmos Design of an 8-Bit 1MS/S Successive Approximation Register ADC
… logic to avoid external high frequency clock, a dynamic comparator to improve linearity and a differential charger-distribution DAC with a monotonic capacitor switching procedure to achieve better power efficiency. This ADC is developed on a 0.18um TSMC process using Cadence Integrated Circuit …
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Low-power SAR ADC for biomedical portable devices
… the primary source of power dissipation is the comparator. Unlike other digital blocks such as control logic and DAC switching, the comparator’s energy consumption does not scale in the same manner with the supply voltage. Reducing power consumption in SAR ADCs with resolutions exceeding 10-bits …
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Energy-efficient data converter design in scaled CMOS technology
… of the low-speed converters including the comparator; 2) techniques to develop high-speed data converters including the reference stabilization; 3) new architecture to improve the efficiency of the capacitance-to-digital converter (CDC). In the first part, a power-efficient 10-bit SAR ADC …