Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 11 of 11 for “"digital calibration"”.
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Digital calibration of nonlinear memory errors in sigma-delta ADCs
Background digital calibration techniques based on an output-referred error model are proposed to linearize sigma-delta (ΣΔ) modulators. A sequential power series (a special form of Volterra series) is found sufficient to model the nonlinear memory errors in a discrete-time integrator (DTI), which …
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Low-power high-performance SAR ADC design with digital calibration techniques
… (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors …
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Feasibility of a 16bit, 3MSPS multibit per stage pipeline ADC using digital calibration
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science; and, Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.
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A pipelined analog-to-digital converter with low-gain, low-bandwidth op-amps
… this thesis presents the shadow-ADC-assisted digital calibration technique. The proposed technique relaxes op-amp performance requirements by removing op-amp-induced charge-transfer errors in the digital domain. A proof-of-concept pipelined ADC has been designed in 28nm FDSOI CMOS technology …
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Circuits and algorithms for pipelined ADCs in scaled CMOS technologies
… issues. First is the development of two blind digital calibration techniques. Decision Boundary Gap Estimation (DBGE) removes static non-linearities and Chopper Offset Estimation (COE) nulls offsets in pipelined ADCs. Second is the development of circuits for a new architecture called …
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Digital ADCs and ultra-wideband RF circuits for energy constrained wireless applications by Denis Clarke Daly.
… much research has focused on developing 'highly digital' circuits and architectures that are tolerant of the increased leakage, variation and degraded voltage headrooms associated with advanced CMOS processes. This thesis presents several highly digital, mixed-signal circuits and architectures …
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An energy efficient CMOS interface to carbon nanotube sensor arrays
… the requirement into a 10-bit Analog-to-Digital Converter (ADC) and a 8-bit Digital-to-Analog Converter (DAC). An extra 1-bit leaves room for any unaccounted subblock performance error. Several system-level all-digital calibration schemes are proposed to account for DAC nonlinearity, ADC …
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A high speed serializer/deserializer design
… with 2V power supply voltage.</p><p>A time-to-digital (TDC) calibration circuit was designed to compensate for the phase mismatches among the multiple phases of the PLL clock using a three dimensional fully depleted silicon on insulator (3D FDSOI) CMOS process. The 3D process separated the …
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Performance enhancement strategies for design and test Optimization of analog and mixed-signal circuits
… analog circuits poses significant challenges for digital-to-analog converters (DACs), which are expected to maintain a linear relationship between their digital input codes and corresponding analog outputs. This linearity, along with other crucial properties, is often compromised by the area …
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A SEIR-based ADC built-in-self-test and its application in ADC self-calibration
… used to measure DC performance of analog to digital converters (ADCs). It comes with high test equipment cost. An ADC built-in-self-test (BIST) is an attractive solution. However the stringent linearity requirement for an on-chip signal generator has made it prohibitive. The stimulus error …
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Power-Efficient Voltage-Mode RF Front-End Using Quantized Analog Signal Processing
… down to 1.6 mW for the LO), 3) an automated calibration platform was developed for the QA receiver where it significantly increased the linearity performance (e.g., up to 33 dB improvement for both third-order and second-order intermodulation products compared to non-calibrated), and 4) a …