Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 6 of 6 for “"deterministic jitter"”.
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Techniques for low jitter clock multiplication
… Loops (MDLL), offer significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is achieved by introducing the reference signal directly into their voltage controlled oscillators (VCO) to realign the phase to the clean reference. However, the typical cost of this benefit …
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Models predicting the performance of IC component or PCB channel during electromagnetic interference
… cover the prediction of the characteristics of jitter due to crosstalk and due to simultaneous switching noise, and covers susceptibility of delay locked loop (DLL) to electromagnetic interference.</p> <p>In the first paper, an improved tail-fit de-convolution method is proposed for …
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High-Speed Low-Voltage Line Driver for SerDes Applications
… has a power consumption of 4.54m W /Gbps. The Deterministic Jitter added by the line driver is 12.9ps.
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Clock multiplication techniques for high-speed I/Os
Generation of a low-jitter, high-frequency clock from a low-frequency reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by …
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Systems and circuits for broadband contactless and wireline transceivers
… technique is introduced to fully detect the deterministic jitter (DJ) in the output clock at much lower speeds with minimal power overhead. An orthogonal 3-path LMS-based adaptation algorithm is implemented to suppress the DJ using 5 fs-resolution digital to time converters (DTCs) at the …
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Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System
… clock generators are required to provide low jitter and high precision clocks in fully integrated image reject receivers and an ultra-wide tunability in time-interleaved applications. We explore several circuit design techniques and implementations of low jitter clock generator in this thesis. …