Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 99 for “"debug"”.
-
A user interface for algorithmic debug
… share key architectural, test, and debug knowledge. By enabling system experts to automate the detection of common simulation failures, VASE allows the engineers who are inheriting a subsystem to instantly have access to their expertise whenever a simulation failure occurs. The VASE …
-
Debug Tutor: Automated Deliberate Debugging Practice for Undergraduate Programmers
Novice programmers struggle with debugging. Despite a rich literature of research on the effectiveness of teaching debugging, debugging is often not taught systematically in computer science curricula. This thesis presents the Debug Tutor, an automated debugging tutor for explicit debugging …
-
Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug
… FPGAs within the scope of a traditional software debugger. This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a …
-
Algorithms and Low Cost Architectures for Trace Buffer-Based Silicon Debug
An effective silicon debug technique uses a trace buffer to monitor and capture a portion of the circuit response during its functional, post-silicon operation. Due to the limited space of the available trace buffer, selection of the critical trace signals plays an important role in both minimizing …
-
System-level trace signal selection for post-silicon debug using linear programming
… are a often used structure in post-silicon debug that stores the state of a selected signal into an on-chip buffer, where they can be offloaded for a debugger to observe. However, because of area limitations for debug structures on chip and routing concerns, the signals that are selected to …
-
Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers
… structure which help in developing reasoning/ debugging tools. In this thesis, we focus on two such EDA tools using graphs as their underlying structure for circuit information storage • Scan pattern Debugger for Partial Scan Designs • Circuit SAT Bounded Model Checkers We developed a complete …
-
Implementación de la plataforma tecnológica de recomendación como caso de estudio de mejora en la empresa DEBUG S.A.C.
DEBUG S.A.C is a company dedicated to the production of highly specialized software and has no presence in the market for non-specialized products. TRecomiendo is based on the platform of a project developed for a particular customer with the potential to develop to more industries. This platform …
-
Source Level Debugging of Circuits Synthesized from High Level Language Descriptions
… the search for new approaches to the design, debug and verification of circuits. The desire to find more effecient approaches to designing these large FPGA circuits has led to the creation of synthesizing compilers that can create hardware from high-level descriptions based on general purpose …
-
Protocol-directed trace signal selection for post-silicon validation
… post-silicon validation, an effective silicon debug technique is to use an on-chip trace buffer to monitor and capture the circuit response of certain selected signals during its post-silicon operation. However, because of area limitations for debug structures on chip and routing concerns, the …
-
Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity
… be sacrificed for improved implementation and debug turnaround. The PATIS floorplanner enables dynamic modular design, which accelerates non-local changes to the physical layout arising from design exploration and the addition of debug circuitry. We focus in this work on incremental and …
-
EM-ONE : an architecture for reflective commonsense thinking
… by applying "mental critics," procedures that debug problems that exist in the outside world or within EM- ONE itself. Mental critics draw upon commonsense narratives to suggest courses of action, methods for deliberating about the circumstances and consequences of those actions, and--when …
-
Scalable functional validation of next generation SoCs
… challenges include observability enhancement and debug and diagnosis under the constraint of vertical integrations, identifying high-quality verification artifacts among others. In industrial practice, SoC validation is a manual, unsystematic, and ad hoc process that heavily relies on the …
-
Designing a processor in Bluespec
… methodology is proposed to effectively express, debug, and optimize large Bluespec designs.
-
Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test
… internal signal values as possible during debug. To do so, trace buffers have been proposed for enhancing the observability of internal signals during post-silicon debug. Trace Buffers are used to trace (record the values of) the internal signals in real-time when chip is in its normal …
-
Python Semantic Investigator : an interactive debugger with reversible state
… so is intended to help novice students learn to debug more effectively.
-
Reasoning system for real time reactive systems
… One of the main uses of the simulation tool is debugging. The Reasoning System is a very good complement of the simulation tool. The scope of this thesis is the study of a Reasoning System that can be used along with the simulation tool to help debug the design and verify system properties …
-
Proactively detecting unreliable tests
… the developers’ workflow and having developers debug not their software but rather the test code or infrastructure. This dissertation presents two techniques to enable developers to more easily and proactively detect and debug unreliable tests early, before they become a problem and slow down …
-
Supercomputing visualization made simple
… researchers' goals to create, analyze, test and debug numerical algorithms in supercomputing world.
-
Hardware Architectures for Low-power In-Situ Monitoring of Wireless Embedded Systems
… systems severely limits the ability to access, debug, and control device operation after deployment—post-deployment or in-situ visibility. It is intuitive that the more information we have about a system’s operation after deployment, the better/faster we can respond upon the detection of …
-
Language & tools for context-aware biology
… responsible making protocols difficult to debug and laboratory practice hard to learn. In this thesis, we describe an open Protocol Descriptor Language (PDL) and system to enable a context-rich, quantitative approach to biological research. We detail the development of a closed-loop …
Page 1 of 5