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Showing 1 to 20 of 56 for “"computer architectures"”.

  1. Digital image compression on parallel computer architectures

    … the number of bits required to store an image in computer memory and/or transmit it over a communication link. Over the past decade advancements in technology have spawned many applications of digital imaging, such as photo videotex, desktop publishing, graphics arts, colour facsimile, newspaper …

    vu-aus Repository record for Digital image compression on parallel computer architectures (opens in a new tab)

  2. Formal Representation of Computer Architectures (Simulation, Language, Hardware)

    This thesis is on the subject of computer architecture, specifically in the area of architecture representation. The main results are that it is possible to represent computer architectures in a formal fashion and that there are theoretical and practical advantages to considering architecture in …

    uiuc Repository record for Formal Representation of Computer Architectures (Simulation, Language, Hardware) (opens in a new tab)

  3. Synthesis and evaluation of fault-tolerant quantum computer architectures

    … that applies to realistic models of quantum computer architectures, and demonstrate this technique numerically. We clarify a central problem for experimental approaches to fault-tolerance evaluation--namely, distinguishing between potentially optimistic pseudo-thresholds and actual thresholds …

    mit Repository record for Synthesis and evaluation of fault-tolerant quantum computer architectures (opens in a new tab)

  4. Development of Advanced Nodal Diffusion Methods for Modern Computer Architectures

    … on sequential, vector, and vector-concurrent computers. Three dimensional realistic benchmark problems can be solved in vectorized mode in less than 0.73 s (33.86 Mflops) on a Cray X-MP/48. Vector-concurrent implementations yield speedups as high as 9.19 on an Alliant FX/8. These results show …

    uiuc Repository record for Development of Advanced Nodal Diffusion Methods for Modern Computer Architectures (opens in a new tab)

  5. Performance Modeling of Single Processor and Multi-Processor Computer Architectures

    Determining the optimum computer architecture configuration for a specific application or a generic algorithm is a difficult task. The complexity involved in today's computer architectures and systems makes it more difficult and expensive to easily and economically implement and test full …

    vt Repository record for Performance Modeling of Single Processor and Multi-Processor Computer Architectures (opens in a new tab)

  6. Fault-tolerant quantum computer architectures using hierarchies of quantum error-correcting codes

    Quantum computers have been shown to efficiently solve a class of problems for which no efficient solution is otherwise known. Physical systems can implement quantum computation, but devising realistic schemes is an extremely challenging problem largely due to the effect of noise. A quantum …

    mit Repository record for Fault-tolerant quantum computer architectures using hierarchies of quantum error-correcting codes (opens in a new tab)

  7. Progress Towards the Development of a Time-Dependent Nodal Diffusion Method for Advanced Computer Architectures

    Made available in DSpace on 2017-07-06T18:55:23Z (GMT). No. of bitstreams: 3 Miller_Harry_E_Jr_MS.pdf: 42770881 bytes, checksum: 0cffdc138b1a8aadbfc0fdbb6a49bddd (MD5) Miller_Harry_E_Jr_MS_ABS.pdf: 584535 bytes, checksum: 82ec036c4639f217c47c26b95fda01d0 (MD5) license.txt: 4813 bytes, checksum: …

    uiuc Repository record for Progress Towards the Development of a Time-Dependent Nodal Diffusion Method for Advanced Computer Architectures (opens in a new tab)

  8. Massively parallel algorithms for method of characteristics neutral particle transport on shared memory computer architectures

    … past 20 years, parallel computing has enabled computers to grow ever larger and more powerful while scientific applications have advanced in sophistication and resolution. This trend is being challenged, however, as the power consumption for conventional parallel computing architectures has …

    mit Repository record for Massively parallel algorithms for method of characteristics neutral particle transport on shared memory computer architectures (opens in a new tab)

  9. VISTA : a visualization tool for computer architects

    As computer architectures continue to grow in complexity, software developers and hardware engineers cope with the increasing complexity by developing proprietary applications, simulations and tool sets to understand the behavior of these complex systems. Although the field of information …

    mit Repository record for VISTA : a visualization tool for computer architects (opens in a new tab)

  10. Parallel and Adaptive Galerkin Methods for Radiative Transfer Problems

    … developed and their implementation on parallel computer architectures is discussed. A posteriori error estimates allow for efficient grid adaptation in two and three space dimensions.

    heid-diss Repository record for Parallel and Adaptive Galerkin Methods for Radiative Transfer Problems (opens in a new tab)

  11. Hardware thread management modeling for precision timed processors

    … Certain areas of research seek to modify modern computer architecture to meet the needs of CPS applications. Moreover, specific modifications in current computer architecture have produced newer computer architectures and processors, such as precision timed (PRET) processors. This thesis focuses …

    utc Repository record for Hardware thread management modeling for precision timed processors (opens in a new tab)

  12. Decoherence and Dynamical Decoupling in Solid-State Spin Qubits

    … spin bath relevant to semiconductor quantum computer architectures. In the presence of an external magnetic field and at low temperatures, the dominant decoherence mechanism is the spectral diffusion of the qubit spin resonance frequency due to the temporally fluctuating random magnetic field …

    maryland Repository record for Decoherence and Dynamical Decoupling in Solid-State Spin Qubits (opens in a new tab)

  13. Games meet Concurrency: Algorithms and Hardness

    … performance gains has led to the prominence of computer architectures with high degrees of parallelism and memory cache hierarchies. However, there are still many challenges to designing efficient algorithms and understanding the complexity of fundamental problems in these new models of …

    mit Repository record for Games meet Concurrency: Algorithms and Hardness (opens in a new tab)

  14. Topology Optimization with Unstructured Meshes on Graphics Processing Units (GPUs)

    … for unstructured meshes in massively parallel computer architectures, more speci cally on Graphics Processing Units or GPUs. Algorithms for every step in these methods are proposed and benchmarked with varied results. The ultimate goal of this work is to speed up the topology optimization …

    uiuc Repository record for Topology Optimization with Unstructured Meshes on Graphics Processing Units (GPUs) (opens in a new tab)

  15. Scalability Analysis of Synchronous Data-Parallel Artificial Neural Network (ANN) Learners

    … datasets; and (2) the availability of new computer architectures for which ANN implementations are orders of magnitude more efficient. In this thesis, I present research on two aspects of the second development. First, I present a portable, open source implementation of ANNs in OpenCL and …

    vt Repository record for Scalability Analysis of Synchronous Data-Parallel Artificial Neural Network (ANN) Learners (opens in a new tab)

  16. Efficient memory and GPU operations for Tiramisu compiler

    The increasing complexity of computer architectures with different memory hierarchies and parallelism characteristics makes generating efficient code a difficult task. Achieving high performance requires complex schedules and data layout transformations which might not be easy to express in a low …

    mit Repository record for Efficient memory and GPU operations for Tiramisu compiler (opens in a new tab)

  17. Processor parallelism considerations and memory latency reduction in shared memory multiprocessors

    A wide variety of computer architectures have been proposed to exploit parallelism at different granularities. These architectures have significant differences in instruction scheduling constraints, memory latencies, and synchronization overhead, making it difficult to determine which architecture …

    uiuc Repository record for Processor parallelism considerations and memory latency reduction in shared memory multiprocessors (opens in a new tab)

  18. Accelerating genomic sequence alignment using high performance reconfigurable computers

    … and power efficiency gains over conventional computer architectures for a subset of high performance computing applications. In this thesis, we investigate the potential of reconfigurable computers to accelerate genomic sequence alignment specifically for genome sequencing applications. We …

    cape-town Repository record for Accelerating genomic sequence alignment using high performance reconfigurable computers (opens in a new tab)

  19. Towards automatic migration of sequential kernels : Numba to PyKokkos

    … performant frameworks requires knowledge about computer architectures, familiarity with parallel programming, and getting across a steep learning curve. Recent work on PyKokkos has bridged this gap considerably by bringing HPC to Python. While PyKokkos provides remarkable performance, switching …

    texas Repository record for Towards automatic migration of sequential kernels : Numba to PyKokkos (opens in a new tab)

  20. Bus scheduling implementation on the cell processor

    … cache and front side bus, in the modern computer architectures, the estimation of a tight bound, worst case execution time (WCET) is difficult. The new generation computer architecture, Cell Broadband Engine Architecture (CBEA), has a software controlled front side bus (i.e. Element …

    uiuc Repository record for Bus scheduling implementation on the cell processor (opens in a new tab)

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